FPGA Central

Hello,
I'm trying to implement a bidirectional bus. I've declared the port as
inout std_logic_vector, and the simulation shows only "UUU...". Any
idea how I control the inout bus?

read: process(clk2x)
begin
if rising_edge(clk2x) then
if read_data = '1' then
u_data_o <= ddr_dq;
u_data_valid <= '1';
else
u_data_o <= (others => '0');
u_data_valid <= '0';
end if;
end if;
end process read;

write: process(clk2x)
begin
if falling_edge(clk2x) then
if write_data = '1' then
ddr_dq <= u_data_i;
ddr_dqs <= clkstr;
elsif read_data = '0' then
ddr_dq <= (others => 'Z');
ddr_dqs <= 'Z';
end if;
end if;
end process write;

<[email protected]> wrote in message
news:[email protected] oups.com...
> Hello,
> I'm trying to implement a bidirectional bus. I've declared the port as
> inout std_logic_vector, and the simulation shows only "UUU...". Any
> idea how I control the inout bus?
>
> read: process(clk2x)
> begin
> if rising_edge(clk2x) then
> if read_data = '1' then
> u_data_o <= ddr_dq;
> u_data_valid <= '1';
> else
> u_data_o <= (others => '0');
> u_data_valid <= '0';
> end if;
> end if;
> end process read;
>
> write: process(clk2x)
> begin
> if falling_edge(clk2x) then
> if write_data = '1' then
> ddr_dq <= u_data_i;
> ddr_dqs <= clkstr;
> elsif read_data = '0' then
>
**********
Are you sure you meant 'read_data' there? Else it only tristates when you're
not reading. I think.
HTH, Syms.
**********
>
> ddr_dq <= (others => 'Z');
> ddr_dqs <= 'Z';
> end if;
> end if;
> end process write;
>

The inout buses are controlled in the same manner as in or out buses
Make sure that the ddr_dq and u_data_i are getting values at the
previous edge of when u expects the data in the inout bus.

Put the data busses out of the process. Write it as a concurren
statement and use one output_enable(OE) signal to control the inou
bus

inout_bus <= out_bus when OE = '1' ELSE (OTHERS => 'Z')
in_bus <= inout_bus

In this way you write to the INOUT only when OE is 1
The in_bus is always reading the INOUT