FPGA Central

Hello all,

I am having a strange thing happening.
This was not urgent, so i kinda did not post it previously...

I have a design synthesized for XC2V2000-FG686-4 or XC2V3000-FG686-4

(one) When running the entire ISE flow, everything is smooth, the PROM files
are generated
using two devices 1804v, one 100% full and another 65% full. FPGA is fully
functional and everything is working.

(two) When running the same using command line, i get that PROM files are
generated
using two devices 1804v, one 100% full and another 62% full. When
programming FPGA with this configuration,
nothing is working. the LEDs which blink once a second per different clock
domains are "dead"...

I have noticed this with both ISE 6.3 and 7.1

The question is what the hell is happening here?

Thank you all for your time and attention

Sincerely,
Vladislav

One more thing to add I am using WinXP

Vladislav


"Vladislav Muravin" <[email protected]> wrote in message
news:[email protected]. ..
> Hello all,
>
> I am having a strange thing happening.
> This was not urgent, so i kinda did not post it previously...
>
> I have a design synthesized for XC2V2000-FG686-4 or XC2V3000-FG686-4
>
> (one) When running the entire ISE flow, everything is smooth, the PROM
> files are generated
> using two devices 1804v, one 100% full and another 65% full. FPGA is fully
> functional and everything is working.
>
> (two) When running the same using command line, i get that PROM files are
> generated
> using two devices 1804v, one 100% full and another 62% full. When
> programming FPGA with this configuration,
> nothing is working. the LEDs which blink once a second per different clock
> domains are "dead"...
>
> I have noticed this with both ISE 6.3 and 7.1
>
> The question is what the hell is happening here?
>
> Thank you all for your time and attention
>
> Sincerely,
> Vladislav
>

Vladislav Muravin wrote:
> One more thing to add I am using WinXP
>
> Vladislav
>
>
> "Vladislav Muravin" <[email protected]> wrote in message
> news:[email protected]. ..
>
>>Hello all,
>>
>>I am having a strange thing happening.
>>This was not urgent, so i kinda did not post it previously...
>>
>>I have a design synthesized for XC2V2000-FG686-4 or XC2V3000-FG686-4
>>
>>(one) When running the entire ISE flow, everything is smooth, the PROM
>>files are generated
>>using two devices 1804v, one 100% full and another 65% full. FPGA is fully
>>functional and everything is working.
>>
>>(two) When running the same using command line, i get that PROM files are
>>generated
>>using two devices 1804v, one 100% full and another 62% full. When
>>programming FPGA with this configuration,
>>nothing is working. the LEDs which blink once a second per different clock
>>domains are "dead"...
>>
>>I have noticed this with both ISE 6.3 and 7.1
>>
>>The question is what the hell is happening here?
>>
>>Thank you all for your time and attention
>>
>>Sincerely,
>>Vladislav
>>
>
>
>

Startup clock selection? .UCF file not included in command line version?
(happened to me, resulted in a smoked board )

Vladislav Muravin wrote:
> Hello all,
>
> I am having a strange thing happening.
> This was not urgent, so i kinda did not post it previously...
>
> I have a design synthesized for XC2V2000-FG686-4 or XC2V3000-FG686-4
>
> (one) When running the entire ISE flow, everything is smooth, the PROM files
> are generated
> using two devices 1804v, one 100% full and another 65% full. FPGA is fully
> functional and everything is working.
>
> (two) When running the same using command line, i get that PROM files are
> generated
> using two devices 1804v, one 100% full and another 62% full. When
> programming FPGA with this configuration,
> nothing is working. the LEDs which blink once a second per different clock
> domains are "dead"...
>
> I have noticed this with both ISE 6.3 and 7.1
>
> The question is what the hell is happening here?

I just spent some time today building a Makefile for one of my chips.
When I got to promgen, I got a complaint that my design wouldn't fit
into the chosen PROM!

Turns out that I told it the wrong part type in one of the scripts. I
ended up running the whole process in ISE and checking the command
lines for each pieces and compared that to what my Makefile was calling
out.

-a

Hey Jim,

UCF file is included.
start-up clock selection... hmmmmmmmmmm....
I just used the same file that is generated through GUI, is it good enough?

Many thanks

Vladislav

"Jim George" <[email protected]> wrote in message
news:[email protected]...
> Vladislav Muravin wrote:
>> One more thing to add I am using WinXP
>>
>> Vladislav
>>
>>
>> "Vladislav Muravin" <[email protected]> wrote in message
>> news:[email protected]. ..
>>
>>>Hello all,
>>>
>>>I am having a strange thing happening.
>>>This was not urgent, so i kinda did not post it previously...
>>>
>>>I have a design synthesized for XC2V2000-FG686-4 or XC2V3000-FG686-4
>>>
>>>(one) When running the entire ISE flow, everything is smooth, the PROM
>>>files are generated
>>>using two devices 1804v, one 100% full and another 65% full. FPGA is
>>>fully functional and everything is working.
>>>
>>>(two) When running the same using command line, i get that PROM files are
>>>generated
>>>using two devices 1804v, one 100% full and another 62% full. When
>>>programming FPGA with this configuration,
>>>nothing is working. the LEDs which blink once a second per different
>>>clock domains are "dead"...
>>>
>>>I have noticed this with both ISE 6.3 and 7.1
>>>
>>>The question is what the hell is happening here?
>>>
>>>Thank you all for your time and attention
>>>
>>>Sincerely,
>>>Vladislav
>>>
>>
>>
>>
>
> Startup clock selection? .UCF file not included in command line version?
> (happened to me, resulted in a smoked board )