FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > FPGA

FPGA comp.arch.fpga newsgroup (usenet)

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 10-30-2003, 02:29 AM
Dave
Guest
 
Posts: n/a
Default using extra eeprom space

Hi,
I have a design using a spartanIIE and a xcs02f configuration eeprom. The
eeprom is 89% full (apparently it will always be that way even if I have a
larger design). I wonder if the fpga can use the extra 11% to store and read
data. I only need to store something like 10 bytes of data before the fpga
is powered off, and reading it back upon power up.

Rgds
Dave


Reply With Quote
  #2 (permalink)  
Old 11-13-2003, 10:29 PM
Jon Elson
Guest
 
Posts: n/a
Default Re: using extra eeprom space



Dave wrote:

>Hi,
>I have a design using a spartanIIE and a xcs02f configuration eeprom. The
>eeprom is 89% full (apparently it will always be that way even if I have a
>larger design). I wonder if the fpga can use the extra 11% to store and read
>data. I only need to store something like 10 bytes of data before the fpga
>is powered off, and reading it back upon power up.
>
>

How will you erase what is in the EEPROM without erasing it all? Some
EEPROMS have
that capability, many don't. Any logic controlling this must be outside
the FPGA so
the FPGA can configure itself on power on.

Jon

Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
How to verify register space [email protected] Verilog 2 01-17-2008 06:58 PM
Behavioral model of SPI EEPROM [email protected] Verilog 2 06-12-2006 12:22 PM
Install problem RedHat 7.3 ISE 6.1i - no space available Alan Fitch FPGA 0 09-24-2003 09:45 AM


All times are GMT +1. The time now is 12:54 PM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved