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  #1 (permalink)  
Old 11-30-2007, 02:11 PM
Guest
 
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Default Using DDR RAM on XUP V2Pro board

Hello,

I'd like to ask if there's a way to get the DDR RAM on the XUP V2Pro
board by Digilent up and running without using the PLB DDR controller?
I know here are a few designs for V2Pro, but I'm not an expert in
uding DRAM-s and haven't planned to become one (although I'm starting
to get an impression that without a significant amount of expertise I
won't be able to deal with the problem). The new MIG by Xilinx does
not support older parts, and the previous versions got me confused by
just looking at them. Anyway, it takes more than a headache to
discourage me from trying to get the memory to work, so I've dug out
the parameters of the DIMM module and the IC's mounted on it (I'm
using the 256MB Kingston module sold by Digilent, I've got it with the
board), checked it a few times, passed it to the editor and stumbled
upon the problem with the pins and banks settings (more dialogs, more
options...). I cannot work on this problem during the weekend, but I
just wanted to make sure if it is possible to create a working
controller for my board with the MIG? Does it require any fine-tuning
after implementation? Did anyone try it (and succeeded)? Are there
maybe other, more user-friendly, or maybe even ready-made, tested
soultions? Any help, guidance, directions are appreciated. I don't
want to spend too much time tackling this problem (although I'm aware
it might not be that easy).

Kind regards.
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  #2 (permalink)  
Old 12-01-2007, 12:53 AM
David Binnie
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Posts: n/a
Default Re: Using DDR RAM on XUP V2Pro board

Memory interface gererator 007 provides DDR1 SDRAM and DDR2 SDRAM memory
interfaces for xilinx Virtex2, Virtex2P and Spartan3 FPGAs.It generates
design files(rtl,sdc,ucf )
and documents (Timing,appnotes, user guide) in the usr folder for the
selected options from
the GUI.

Following steps generate DDR1 SDRAM memory interface for, Components, 8 DQs
per DQS, right side of V2P device to 72 bit data.

* Select Memory type DDR1 by clicking the down arrow button.

* Select the Components by checking the Component radio buttons.

* Select the number of DQ bits per DQS 8 by checking the X8 radio buttons.

* Select Family Virtex2P by clicking the down arrow button.

* Select Part 2vp20ff1152 by clicking the down arrow button.

* Select the Speed grade -6 by clicking the button.

* Select the Frequency in MHz 200 by dragging the slider.

* Select the number of controllers to 1 by clicking the down arrow button.

* Select the banks for data and datastrobe by clicking the check box 2 and
3.

* Select the banks for address & control by clicking the check box 6 and 7.

* Enter the WASSO values for banks 2 and 3 by clicking the WASSO Table, if
the WASSO values differ from default values.

* Select the Data bits 72 by clicking the down arrow button.

* To exclude Vrp/Vrn pins for memory interface check the "Reserve Vrp/Vrn
pins " box.

* From Menu "Options", HDL, select Verilog or VHDL.

* From Menu "Options", Design, select Full controller or Physical layer with
data or
Physical layer with data, address and control.

* Click on Show pins.The pins from the selected banks are displayed in the
"Selected pins"
listbox. To reserve some pins,double click it. Also click on "Read reserve
pin ucf"
button to input your constraint file so that the pins will not be used for
memory interface.

* Add button allows the user to add the pins back from the Reserved pins
list for allocating to
memory interface.

* Hierarchy path provides the user for instantiating memory interface with
other designs.

* By default result files are stored in ../usr directoy. Result directory
button allows the
user to save the result files to a selected directory.

* Click on "Generate design" to generate the design files.The files are
created in usr directory.

* Pin compatibility check button allows to generate UCF files across
multiple devices.

* Pin editor option allows the user to select the dq, dqs and no_dpin pins.
Click on Show pins activates the Pin editor.


<[email protected]> wrote in message
news:[email protected]m...
> Hello,
>
> I'd like to ask if there's a way to get the DDR RAM on the XUP V2Pro
> board by Digilent up and running without using the PLB DDR controller?
> I know here are a few designs for V2Pro, but I'm not an expert in
> uding DRAM-s and haven't planned to become one (although I'm starting
> to get an impression that without a significant amount of expertise I
> won't be able to deal with the problem). The new MIG by Xilinx does
> not support older parts, and the previous versions got me confused by
> just looking at them. Anyway, it takes more than a headache to
> discourage me from trying to get the memory to work, so I've dug out
> the parameters of the DIMM module and the IC's mounted on it (I'm
> using the 256MB Kingston module sold by Digilent, I've got it with the
> board), checked it a few times, passed it to the editor and stumbled
> upon the problem with the pins and banks settings (more dialogs, more
> options...). I cannot work on this problem during the weekend, but I
> just wanted to make sure if it is possible to create a working
> controller for my board with the MIG? Does it require any fine-tuning
> after implementation? Did anyone try it (and succeeded)? Are there
> maybe other, more user-friendly, or maybe even ready-made, tested
> soultions? Any help, guidance, directions are appreciated. I don't
> want to spend too much time tackling this problem (although I'm aware
> it might not be that easy).
>
> Kind regards.



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  #3 (permalink)  
Old 12-01-2007, 11:08 AM
Guest
 
Posts: n/a
Default Re: Using DDR RAM on XUP V2Pro board

Believe it or not, I've already read it. I just wanted to ask if there
are any surprises that might happen along the way. Sometimes things
don't work exactly as they should. It's better to know about it
earlier than after two weeks of why-the-hell-desn't-it-work. If anyone
can give me such directions, has implemented successful controller on
this board using MIG, or even points out an alternative solution that
will work for me - that would be great. I am not working on it during
the weekend, so I just thought it would be a good thing to ask.

Kind regards,

Marek.

On 1 Gru, 00:53, "David Binnie" <[email protected]> wrote:
> Memory interface gererator 007 provides DDR1 SDRAM and DDR2 SDRAM memory
> interfaces for xilinx Virtex2, Virtex2P and Spartan3 FPGAs.It generates
> design files(rtl,sdc,ucf )
> and documents (Timing,appnotes, user guide) in the usr folder for the
> selected options from
> the GUI.
>
> Following steps generate DDR1 SDRAM memory interface for, Components, 8 DQs
> per DQS, right side of V2P device to 72 bit data.
>
> * Select Memory type DDR1 by clicking the down arrow button.
>
> * Select the Components by checking the Component radio buttons.
>
> * Select the number of DQ bits per DQS 8 by checking the X8 radio buttons.
>
> * Select Family Virtex2P by clicking the down arrow button.
>
> * Select Part 2vp20ff1152 by clicking the down arrow button.
>
> * Select the Speed grade -6 by clicking the button.
>
> * Select the Frequency in MHz 200 by dragging the slider.
>
> * Select the number of controllers to 1 by clicking the down arrow button.
>
> * Select the banks for data and datastrobe by clicking the check box 2 and
> 3.
>
> * Select the banks for address & control by clicking the check box 6 and 7.
>
> * Enter the WASSO values for banks 2 and 3 by clicking the WASSO Table, if
> the WASSO values differ from default values.
>
> * Select the Data bits 72 by clicking the down arrow button.
>
> * To exclude Vrp/Vrn pins for memory interface check the "Reserve Vrp/Vrn
> pins " box.
>
> * From Menu "Options", HDL, select Verilog or VHDL.
>
> * From Menu "Options", Design, select Full controller or Physical layer with
> data or
> Physical layer with data, address and control.
>
> * Click on Show pins.The pins from the selected banks are displayed in the
> "Selected pins"
> listbox. To reserve some pins,double click it. Also click on "Read reserve
> pin ucf"
> button to input your constraint file so that the pins will not be used for
> memory interface.
>
> * Add button allows the user to add the pins back from the Reserved pins
> list for allocating to
> memory interface.
>
> * Hierarchy path provides the user for instantiating memory interface with
> other designs.
>
> * By default result files are stored in ../usr directoy. Result directory
> button allows the
> user to save the result files to a selected directory.
>
> * Click on "Generate design" to generate the design files.The files are
> created in usr directory.
>
> * Pin compatibility check button allows to generate UCF files across
> multiple devices.
>
> * Pin editor option allows the user to select the dq, dqs and no_dpin pins.
> Click on Show pins activates the Pin editor.
>
> <[email protected]> wrote in message
>
> news:[email protected]m...
>
> > Hello,

>
> > I'd like to ask if there's a way to get the DDR RAM on the XUP V2Pro
> > board by Digilent up and running without using the PLB DDR controller?
> > I know here are a few designs for V2Pro, but I'm not an expert in
> > uding DRAM-s and haven't planned to become one (although I'm starting
> > to get an impression that without a significant amount of expertise I
> > won't be able to deal with the problem). The new MIG by Xilinx does
> > not support older parts, and the previous versions got me confused by
> > just looking at them. Anyway, it takes more than a headache to
> > discourage me from trying to get the memory to work, so I've dug out
> > the parameters of the DIMM module and the IC's mounted on it (I'm
> > using the 256MB Kingston module sold by Digilent, I've got it with the
> > board), checked it a few times, passed it to the editor and stumbled
> > upon the problem with the pins and banks settings (more dialogs, more
> > options...). I cannot work on this problem during the weekend, but I
> > just wanted to make sure if it is possible to create a working
> > controller for my board with the MIG? Does it require any fine-tuning
> > after implementation? Did anyone try it (and succeeded)? Are there
> > maybe other, more user-friendly, or maybe even ready-made, tested
> > soultions? Any help, guidance, directions are appreciated. I don't
> > want to spend too much time tackling this problem (although I'm aware
> > it might not be that easy).

>
> > Kind regards.


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  #4 (permalink)  
Old 12-01-2007, 06:51 PM
Duane Clark
Guest
 
Posts: n/a
Default Re: Using DDR RAM on XUP V2Pro board

[email protected] wrote:
> Believe it or not, I've already read it. I just wanted to ask if there
> are any surprises that might happen along the way. Sometimes things
> don't work exactly as they should. It's better to know about it
> earlier than after two weeks of why-the-hell-desn't-it-work. If anyone
> can give me such directions, has implemented successful controller on
> this board using MIG, or even points out an alternative solution that
> will work for me - that would be great. I am not working on it during
> the weekend, so I just thought it would be a good thing to ask.


I took a look at using the mig generated core for DDR ram on a V2P. I
discovered that in the user interface generated by that tool, some
signals are clocked on the system clock, some on a 90 degree phase
shifted clock, and some on a 180 degree phase shifted clock. Yikes! So
much for an "easy" interface.

I abandoned any attempt to use that core, and instead hacked on the plb
ddr core, simply ignoring the plb interface and adding my own user
interface instead.
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  #5 (permalink)  
Old 12-01-2007, 08:47 PM
David Binnie
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Posts: n/a
Default Re: Using DDR RAM on XUP V2Pro board

Make sure you dont use the DCM and you have to complete the UCF, as for some
reason Xilinx never produced a MIG tool for their V2P board (!)
and then your nearly there, but ours doesn't work yet either so do keep in
touch.


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