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Old 10-24-2003, 12:34 PM
vladimir
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Default Useful examles source code Verilog, VHDL, PLI, FLI, Tcl/Tk embedded interpreter (www.hightech-td.com)

TBGenerator - generates test benches which was described by Verilob or
VHDL. Works with inout ports. Additional tools - convert time to
frequency and frequency to time, create component declaration.
Useful examles source code Verilog, VHDL, PLI, FLI, Tcl/Tk embedded
interpreter.

www.hightech-td.com
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