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  #1 (permalink)  
Old 09-23-2003, 04:01 AM
SneakerNet
Guest
 
Posts: n/a
Default USB 1.1/2.0 Implementation

Hi All

Has anyone successfully implemented USB 2.0 or USB 1.1 protocol in Altera
Device. If yes, can you pls start me off. I'm not able to make any progress
in this. I have found couple of sites in ths area, but always end towards a
brick wall.

Help Pls

Cheerio


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  #2 (permalink)  
Old 09-23-2003, 07:37 AM
Antti Lukats
Guest
 
Posts: n/a
Default Re: USB 1.1/2.0 Implementation

"SneakerNet" <[email protected]> wrote in message news:<[email protected]>...
> Hi All
>
> Has anyone successfully implemented USB 2.0 or USB 1.1 protocol in Altera
> Device. If yes, can you pls start me off. I'm not able to make any progress
> in this. I have found couple of sites in ths area, but always end towards a
> brick wall.


if you dont say what your problem is how could one help?
the USB cores available are working out of box for Xilinx, for altera
you need to change the technology dependant portions and it should
again work.

antti
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  #3 (permalink)  
Old 09-23-2003, 10:39 PM
SneakerNet
Guest
 
Posts: n/a
Default Re: USB 1.1/2.0 Implementation

"Antti Lukats" <[email protected]> wrote in message
news:[email protected] om...
> "SneakerNet" <[email protected]> wrote in message

news:<[email protected]>...
> > Hi All
> >
> > Has anyone successfully implemented USB 2.0 or USB 1.1 protocol in

Altera
> > Device. If yes, can you pls start me off. I'm not able to make any

progress
> > in this. I have found couple of sites in ths area, but always end

towards a
> > brick wall.

>
> if you dont say what your problem is how could one help?
> the USB cores available are working out of box for Xilinx, for altera
> you need to change the technology dependant portions and it should
> again work.
>
> antti


Hi Antti
Thanks for the response. I actually contacted you regarding USB page that
you mentioned in this newsgroup a while back (Japanese language).
Ok firstly regarding USB implementation, the way I see it, there are 3 major
parts, which are:
1. USB Transceiver (to connect the FPGA and the PC)
2. FPGA Implementation
3. Windows App

Now
1. USB Transceiver - I have found out that the Philips PDIUSBP11A is quite
suitable for this job. However if you look at this pdf (which shows the
circuit connection) www.semiconductors.philips.com/acrobat/
applicationnotes/AN10007-01.pdf , on page 5 of this pdf there are 2 circuit
diagrams. I'm not able to understand the difference between upstream and
downstream circuits. Pls help/advice.
2. FPGA Implementation - Antti, you replyed saying (for altera you need to
change the technology dependant portions and it should again work.). What do
you mean by this? Help Again. Where can I download the USB cores to begin
with? Once I can get hold of the USB core, I guess I'll have a starting
point.
3. Windows Implementation - I have no clue with regards to windows drivers.
Any help in this matter would be very greatful.

Thanks guys


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  #4 (permalink)  
Old 09-24-2003, 04:24 AM
rickman
Guest
 
Posts: n/a
Default Re: USB 1.1/2.0 Implementation

SneakerNet wrote:
>
> "Antti Lukats" <[email protected]> wrote in message
> news:[email protected] om...
> > "SneakerNet" <[email protected]> wrote in message

> news:<[email protected]>...
> > > Hi All
> > >
> > > Has anyone successfully implemented USB 2.0 or USB 1.1 protocol in

> Altera
> > > Device. If yes, can you pls start me off. I'm not able to make any

> progress
> > > in this. I have found couple of sites in ths area, but always end

> towards a
> > > brick wall.

> >
> > if you dont say what your problem is how could one help?
> > the USB cores available are working out of box for Xilinx, for altera
> > you need to change the technology dependant portions and it should
> > again work.
> >
> > antti

>
> Hi Antti
> Thanks for the response. I actually contacted you regarding USB page that
> you mentioned in this newsgroup a while back (Japanese language).
> Ok firstly regarding USB implementation, the way I see it, there are 3 major
> parts, which are:
> 1. USB Transceiver (to connect the FPGA and the PC)
> 2. FPGA Implementation
> 3. Windows App
>
> Now
> 1. USB Transceiver - I have found out that the Philips PDIUSBP11A is quite
> suitable for this job. However if you look at this pdf (which shows the
> circuit connection) www.semiconductors.philips.com/acrobat/
> applicationnotes/AN10007-01.pdf , on page 5 of this pdf there are 2 circuit
> diagrams. I'm not able to understand the difference between upstream and
> downstream circuits. Pls help/advice.


I have not looked at the circuits, but upstream is closer to the PC and
so is a "host" type connection while downstream is closer to (or is) the
peripheral. I think there are only very small differences having to do
with initialization protocol.


> 2. FPGA Implementation - Antti, you replyed saying (for altera you need to
> change the technology dependant portions and it should again work.). What do
> you mean by this? Help Again. Where can I download the USB cores to begin
> with? Once I can get hold of the USB core, I guess I'll have a starting
> point.


I think he was saying that he is aware of IP that works in the Xilinx
chips and so would work in any other FPGA. But the coding style may
have used chip specific features (like the 16 bit SRL in the Xilinx
parts). If so, this code may need to be changed to something more
generic for an Altera part. Any Xilinx features that are instantiated
will need to be replaced for sure.

Check www.opencores.org. They have USB 1.1 and 2.0 implementations
available. I don't know if they are vendor specific or not.


> 3. Windows Implementation - I have no clue with regards to windows drivers.
> Any help in this matter would be very greatful.


This depends on your application. I believe there is a generic set of
drivers to support a "human interface device" or similar which means it
works like a mouse or keyboard in terms of sending data in small
packets.

Again, I am not directly experienced with this, but I have been
listening intently when others discuss this here and elsewhere.

--

Rick "rickman" Collins

[email protected]
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
Reply With Quote
  #5 (permalink)  
Old 09-24-2003, 04:32 AM
SneakerNet
Guest
 
Posts: n/a
Default Re: USB 1.1/2.0 Implementation


"rickman" <[email protected]> wrote in message
news:[email protected]
> SneakerNet wrote:
> >
> > "Antti Lukats" <[email protected]> wrote in message
> > news:[email protected] om...
> > > "SneakerNet" <[email protected]> wrote in message

> > news:<[email protected]>...
> > > > Hi All
> > > >
> > > > Has anyone successfully implemented USB 2.0 or USB 1.1 protocol in

> > Altera
> > > > Device. If yes, can you pls start me off. I'm not able to make any

> > progress
> > > > in this. I have found couple of sites in ths area, but always end

> > towards a
> > > > brick wall.
> > >
> > > if you dont say what your problem is how could one help?
> > > the USB cores available are working out of box for Xilinx, for altera
> > > you need to change the technology dependant portions and it should
> > > again work.
> > >
> > > antti

> >
> > Hi Antti
> > Thanks for the response. I actually contacted you regarding USB page

that
> > you mentioned in this newsgroup a while back (Japanese language).
> > Ok firstly regarding USB implementation, the way I see it, there are 3

major
> > parts, which are:
> > 1. USB Transceiver (to connect the FPGA and the PC)
> > 2. FPGA Implementation
> > 3. Windows App
> >
> > Now
> > 1. USB Transceiver - I have found out that the Philips PDIUSBP11A is

quite
> > suitable for this job. However if you look at this pdf (which shows the
> > circuit connection) www.semiconductors.philips.com/acrobat/
> > applicationnotes/AN10007-01.pdf , on page 5 of this pdf there are 2

circuit
> > diagrams. I'm not able to understand the difference between upstream and
> > downstream circuits. Pls help/advice.

>
> I have not looked at the circuits, but upstream is closer to the PC and
> so is a "host" type connection while downstream is closer to (or is) the
> peripheral. I think there are only very small differences having to do
> with initialization protocol.


Thanks for the clarification.

>
>
> > 2. FPGA Implementation - Antti, you replyed saying (for altera you need

to
> > change the technology dependant portions and it should again work.).

What do
> > you mean by this? Help Again. Where can I download the USB cores to

begin
> > with? Once I can get hold of the USB core, I guess I'll have a starting
> > point.

>
> I think he was saying that he is aware of IP that works in the Xilinx
> chips and so would work in any other FPGA. But the coding style may
> have used chip specific features (like the 16 bit SRL in the Xilinx
> parts). If so, this code may need to be changed to something more
> generic for an Altera part. Any Xilinx features that are instantiated
> will need to be replaced for sure.
>
> Check www.opencores.org. They have USB 1.1 and 2.0 implementations
> available. I don't know if they are vendor specific or not.
>


Err.. I found this usb_phy from opencores.org however I'm struggling with
that. The main top layer file has so many I/O's compared to the I/Os of the
PDIUSBP11A, i'm stuck. I'm stuck in the sense that I do not know which pin
will map which one on the transcevier.

>
> > 3. Windows Implementation - I have no clue with regards to windows

drivers.
> > Any help in this matter would be very greatful.

>
> This depends on your application. I believe there is a generic set of
> drivers to support a "human interface device" or similar which means it
> works like a mouse or keyboard in terms of sending data in small
> packets.
>
> Again, I am not directly experienced with this, but I have been
> listening intently when others discuss this here and elsewhere.


Sigh.. I guess I'll join you ..

Thanks for your input.

>
> --
>
> Rick "rickman" Collins
>
> [email protected]
> Ignore the reply address. To email me use the above address with the XY
> removed.
>
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design URL http://www.arius.com
> 4 King Ave 301-682-7772 Voice
> Frederick, MD 21701-3110 301-682-7666 FAX



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  #6 (permalink)  
Old 09-24-2003, 10:19 AM
Antti Lukats
Guest
 
Posts: n/a
Default Re: USB 1.1/2.0 Implementation

"SneakerNet" <[email protected]> wrote in message news:<p43cb.157047
> Has anyone successfully implemented USB 2.0 or USB 1.1 protocol in

[deleted]

USB11T11A FS/LS USB tranceiver

usb_phy (opencores) UTMI interface that connects to USB11T11A

usb1.1 (opencores) connects to usb_phy (opencores) connects to
USB11T1A it is not HID but it will enumerate in hardware iw the USB
host will 'see' it, but ther is no host software provide

usb (japanase desing) full HID USB core includes USB11T1A model) can
directly be connected to usb D+ D- pins! (no tranceiver chip), there
is some VB test program to talk to the core (as it is HID peripheral)

antti
PS I am afraid you have todo some homework cant do it for you
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  #7 (permalink)  
Old 09-24-2003, 10:38 PM
SneakerNet
Guest
 
Posts: n/a
Default Re: USB 1.1/2.0 Implementation

Hi Antti
Thanks for the response.
haha. I don't expect anyone to do work for me, othwersie I won't learn
anything, but I wouldn't mind some guidance along the way from you guys..
Anyway I need to ask 2 questions regarding your reply.
1. When you say USB11T11A, do you mean the Philips tranceiver PDIUSBP11A? If
no then I'm sorry but i'm not able to find anything on USB11T11A. Have I
gone blind?
2. Regarding the usb (japanese design), I have ended up towards a brick
wall. What I mean to say is, I have been looking at the design for couple of
hours and there are 4 components that I'm not sure what they do. The main
problem is that the code was written for a Xilinx component and because I'm
using Altera component, I'm do not have the librabires that these component
are using.
Firstly the library defined is (which is for Xilinx only (pls correct me if
i'm wrong))
library unisim;
use unisim.vcomponents.all;

and the 4 components that are using this library are
u_DLL : CLKDLL
port map ( CLKIN => CLKINM,
CLKFB => GCLK,
RST => RST,
CLK0 => GCLKM,
CLK2X => CLKM,
LOCKED => LOCK
);

u_GCLK : BUFG
port map ( I => GCLKM,
O => GCLK
);

u_CLK : BUFG
port map ( I => CLKM,
O => CLK
);

u_CLKIN : IBUFG
port map ( I => CLKIN,
O => CLKINM
);

If you can explain me how I can replace these components for Altera design,
I will have a step to progress. If I can get past this point, then I have
something to try on the chip and play around. My problem is that right now I
can't go past compiling as Quartus doesn't recognize these components (or
the library). Pls Advice

Thanks again

Regards


"Antti Lukats" <[email protected]> wrote in message
news:[email protected] om...
> "SneakerNet" <[email protected]> wrote in message news:<p43cb.157047
> > Has anyone successfully implemented USB 2.0 or USB 1.1 protocol in

> [deleted]
>
> USB11T11A FS/LS USB tranceiver
>
> usb_phy (opencores) UTMI interface that connects to USB11T11A
>
> usb1.1 (opencores) connects to usb_phy (opencores) connects to
> USB11T1A it is not HID but it will enumerate in hardware iw the USB
> host will 'see' it, but ther is no host software provide
>
> usb (japanase desing) full HID USB core includes USB11T1A model) can
> directly be connected to usb D+ D- pins! (no tranceiver chip), there
> is some VB test program to talk to the core (as it is HID peripheral)
>
> antti
> PS I am afraid you have todo some homework cant do it for you



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  #8 (permalink)  
Old 09-25-2003, 03:22 AM
rickman
Guest
 
Posts: n/a
Default Re: USB 1.1/2.0 Implementation

SneakerNet wrote:
>
> Hi Antti
> Thanks for the response.
> haha. I don't expect anyone to do work for me, othwersie I won't learn
> anything, but I wouldn't mind some guidance along the way from you guys..
> Anyway I need to ask 2 questions regarding your reply.
> 1. When you say USB11T11A, do you mean the Philips tranceiver PDIUSBP11A? If
> no then I'm sorry but i'm not able to find anything on USB11T11A. Have I
> gone blind?
> 2. Regarding the usb (japanese design), I have ended up towards a brick
> wall. What I mean to say is, I have been looking at the design for couple of
> hours and there are 4 components that I'm not sure what they do. The main
> problem is that the code was written for a Xilinx component and because I'm
> using Altera component, I'm do not have the librabires that these component
> are using.
> Firstly the library defined is (which is for Xilinx only (pls correct me if
> i'm wrong))
> library unisim;
> use unisim.vcomponents.all;
>
> and the 4 components that are using this library are
> u_DLL : CLKDLL
> port map ( CLKIN => CLKINM,
> CLKFB => GCLK,
> RST => RST,
> CLK0 => GCLKM,
> CLK2X => CLKM,
> LOCKED => LOCK
> );
>
> u_GCLK : BUFG
> port map ( I => GCLKM,
> O => GCLK
> );
>
> u_CLK : BUFG
> port map ( I => CLKM,
> O => CLK
> );
>
> u_CLKIN : IBUFG
> port map ( I => CLKIN,
> O => CLKINM
> );
>
> If you can explain me how I can replace these components for Altera design,
> I will have a step to progress. If I can get past this point, then I have
> something to try on the chip and play around. My problem is that right now I
> can't go past compiling as Quartus doesn't recognize these components (or
> the library). Pls Advice


This is something I know a bit more about. These are all clock
components. CLKDLL is a DLL (Delay Locked Loop) like a PLL only more
Xilinx like The Altera parts have PLLs depending on the part. I
don't know if this is required or just used to allow different external
and internal clock rates.

The BUFG and IBUFG are just clock buffers. They are used to drive the
internal clock distribution networks. Altera should have equivalent
components or you may not need to instantiate them since they are
typically locked to a given pin and should be inferred by most tools.
Read up a bit on the Xilinx and Altera chips and this will all be very
clear.

--

Rick "rickman" Collins

[email protected]
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
Reply With Quote
  #9 (permalink)  
Old 09-30-2003, 04:27 AM
Paul Leventis
Guest
 
Posts: n/a
Default Re: USB 1.1/2.0 Implementation

Hi SneakerNet,

I just noticed we have VERY handy application note for you -- AN307
(available on www.altera.com) describes how to migrate from a Xilinx design
to an Altera design. There is a section dedicated to DLL to PLL conversion
that should be able to help you out. Below is my attempt at explaining
things before I found this app note.

In Altera's FPGAs, we've got PLLs, which provide a superset of the CLKDLL
function you're trying to use. You'd want to setup your PLL to use CLKIN as
its input inclk0, hook up the C0 port to GCLK signal and C1 port to CLK
signal, don't apply any phase shift, and use the C0 port to compensate the
PLL output. Connect RST to the areset port, and LOCKED to the locked port.
You'll want to setup your C1 port to have a 2x frequency multiplier on it.
The Lock and Reset signals have some sort of equivalent that I can't recall.
You can do this all through the allpll megafunction.

The BUFGs are not necessary in Altera parts. In Xilinx parts, these buffers
are needed to explicitly indicate that you want a signal to be driven onto
the global clock network. Quartus allows you to make "global" assignments
to nets, but it automatically promotes anything it finds that looks like a
clock net, as well as high-fanout or asynchronous signals if there are
enough global clocks available. The PLL output nets will be automatically
promoted to global clock nets for you, and the PLL input will be assigned to
the associated input clock pin.

Also, I should point out that there are four USB cores listed on our
Intellectual Property page (www.altera.com) under Interfaces & Peripherals
under USB. All are available for free trial under our OpenCore evaluation
program.

Regards,

Paul Leventis
Altera Corp.


"SneakerNet" <[email protected]> wrote in message
news:[email protected]
> Hi Antti
> Thanks for the response.
> haha. I don't expect anyone to do work for me, othwersie I won't learn
> anything, but I wouldn't mind some guidance along the way from you guys..
> Anyway I need to ask 2 questions regarding your reply.
> 1. When you say USB11T11A, do you mean the Philips tranceiver PDIUSBP11A?

If
> no then I'm sorry but i'm not able to find anything on USB11T11A. Have I
> gone blind?
> 2. Regarding the usb (japanese design), I have ended up towards a brick
> wall. What I mean to say is, I have been looking at the design for couple

of
> hours and there are 4 components that I'm not sure what they do. The main
> problem is that the code was written for a Xilinx component and because

I'm
> using Altera component, I'm do not have the librabires that these

component
> are using.
> Firstly the library defined is (which is for Xilinx only (pls correct me

if
> i'm wrong))
> library unisim;
> use unisim.vcomponents.all;
>
> and the 4 components that are using this library are
> u_DLL : CLKDLL
> port map ( CLKIN => CLKINM,
> CLKFB => GCLK,
> RST => RST,
> CLK0 => GCLKM,
> CLK2X => CLKM,
> LOCKED => LOCK
> );
>
> u_GCLK : BUFG
> port map ( I => GCLKM,
> O => GCLK
> );
>
> u_CLK : BUFG
> port map ( I => CLKM,
> O => CLK
> );
>
> u_CLKIN : IBUFG
> port map ( I => CLKIN,
> O => CLKINM
> );
>
> If you can explain me how I can replace these components for Altera

design,
> I will have a step to progress. If I can get past this point, then I have
> something to try on the chip and play around. My problem is that right now

I
> can't go past compiling as Quartus doesn't recognize these components (or
> the library). Pls Advice
>
> Thanks again
>
> Regards
>
>
> "Antti Lukats" <[email protected]> wrote in message
> news:[email protected] om...
> > "SneakerNet" <[email protected]> wrote in message news:<p43cb.157047
> > > Has anyone successfully implemented USB 2.0 or USB 1.1 protocol in

> > [deleted]
> >
> > USB11T11A FS/LS USB tranceiver
> >
> > usb_phy (opencores) UTMI interface that connects to USB11T11A
> >
> > usb1.1 (opencores) connects to usb_phy (opencores) connects to
> > USB11T1A it is not HID but it will enumerate in hardware iw the USB
> > host will 'see' it, but ther is no host software provide
> >
> > usb (japanase desing) full HID USB core includes USB11T1A model) can
> > directly be connected to usb D+ D- pins! (no tranceiver chip), there
> > is some VB test program to talk to the core (as it is HID peripheral)
> >
> > antti
> > PS I am afraid you have todo some homework cant do it for you

>
>



Reply With Quote
  #10 (permalink)  
Old 09-30-2003, 05:22 AM
SneakerNet
Guest
 
Posts: n/a
Default Re: USB 1.1/2.0 Implementation

Hello again Paul ;o)

LOL, tell you what, I already cracked it. I found that document sometime
back now *grins*.
And I also cracked that the CLKDLL is just a pll *grins again* and thus I
had posted another msg (which you have already replied before) but once
again I beat you to it. I cracked it before you replied ;o).

Anyway thanks for taking time in explaning the Xilinx components.
Regarding the free USB Cores from Altera website.
Service I would give umm 10% *no offence*. I had to log into that page and
request the core nearly 10 times before someone contacted me from Altera.
Then after 2-3 days they told me that USB 2.0 core is not functional so i
asked for usb 1.1 core. Then they asked me hundreds of questions of why/what
for/how long etc etc. When I finally got it, it was only licenced for a
month (which passes by just like that as I'm working on this USB project
part time.
Anyway I found a site that had the full VHDL USB core free of cost (without
any need for any hardware). I'm stuck at the windows driver now. Rest is all
ready to go..

Any help on how to install a generic usb driver?

Thanks for your response Paul.
Bye

"Paul Leventis" <[email protected]> wrote in message
news:[email protected] able.rogers.com...
> Hi SneakerNet,
>
> I just noticed we have VERY handy application note for you -- AN307
> (available on www.altera.com) describes how to migrate from a Xilinx

design
> to an Altera design. There is a section dedicated to DLL to PLL

conversion
> that should be able to help you out. Below is my attempt at explaining
> things before I found this app note.
>
> In Altera's FPGAs, we've got PLLs, which provide a superset of the CLKDLL
> function you're trying to use. You'd want to setup your PLL to use CLKIN

as
> its input inclk0, hook up the C0 port to GCLK signal and C1 port to CLK
> signal, don't apply any phase shift, and use the C0 port to compensate the
> PLL output. Connect RST to the areset port, and LOCKED to the locked

port.
> You'll want to setup your C1 port to have a 2x frequency multiplier on it.
> The Lock and Reset signals have some sort of equivalent that I can't

recall.
> You can do this all through the allpll megafunction.
>
> The BUFGs are not necessary in Altera parts. In Xilinx parts, these

buffers
> are needed to explicitly indicate that you want a signal to be driven onto
> the global clock network. Quartus allows you to make "global" assignments
> to nets, but it automatically promotes anything it finds that looks like a
> clock net, as well as high-fanout or asynchronous signals if there are
> enough global clocks available. The PLL output nets will be automatically
> promoted to global clock nets for you, and the PLL input will be assigned

to
> the associated input clock pin.
>
> Also, I should point out that there are four USB cores listed on our
> Intellectual Property page (www.altera.com) under Interfaces & Peripherals
> under USB. All are available for free trial under our OpenCore evaluation
> program.
>
> Regards,
>
> Paul Leventis
> Altera Corp.
>
>
> "SneakerNet" <[email protected]> wrote in message
> news:[email protected]
> > Hi Antti
> > Thanks for the response.
> > haha. I don't expect anyone to do work for me, othwersie I won't learn
> > anything, but I wouldn't mind some guidance along the way from you

guys..
> > Anyway I need to ask 2 questions regarding your reply.
> > 1. When you say USB11T11A, do you mean the Philips tranceiver

PDIUSBP11A?
> If
> > no then I'm sorry but i'm not able to find anything on USB11T11A. Have I
> > gone blind?
> > 2. Regarding the usb (japanese design), I have ended up towards a brick
> > wall. What I mean to say is, I have been looking at the design for

couple
> of
> > hours and there are 4 components that I'm not sure what they do. The

main
> > problem is that the code was written for a Xilinx component and because

> I'm
> > using Altera component, I'm do not have the librabires that these

> component
> > are using.
> > Firstly the library defined is (which is for Xilinx only (pls correct me

> if
> > i'm wrong))
> > library unisim;
> > use unisim.vcomponents.all;
> >
> > and the 4 components that are using this library are
> > u_DLL : CLKDLL
> > port map ( CLKIN => CLKINM,
> > CLKFB => GCLK,
> > RST => RST,
> > CLK0 => GCLKM,
> > CLK2X => CLKM,
> > LOCKED => LOCK
> > );
> >
> > u_GCLK : BUFG
> > port map ( I => GCLKM,
> > O => GCLK
> > );
> >
> > u_CLK : BUFG
> > port map ( I => CLKM,
> > O => CLK
> > );
> >
> > u_CLKIN : IBUFG
> > port map ( I => CLKIN,
> > O => CLKINM
> > );
> >
> > If you can explain me how I can replace these components for Altera

> design,
> > I will have a step to progress. If I can get past this point, then I

have
> > something to try on the chip and play around. My problem is that right

now
> I
> > can't go past compiling as Quartus doesn't recognize these components

(or
> > the library). Pls Advice
> >
> > Thanks again
> >
> > Regards
> >
> >
> > "Antti Lukats" <[email protected]> wrote in message
> > news:[email protected] om...
> > > "SneakerNet" <[email protected]> wrote in message news:<p43cb.157047
> > > > Has anyone successfully implemented USB 2.0 or USB 1.1 protocol in
> > > [deleted]
> > >
> > > USB11T11A FS/LS USB tranceiver
> > >
> > > usb_phy (opencores) UTMI interface that connects to USB11T11A
> > >
> > > usb1.1 (opencores) connects to usb_phy (opencores) connects to
> > > USB11T1A it is not HID but it will enumerate in hardware iw the USB
> > > host will 'see' it, but ther is no host software provide
> > >
> > > usb (japanase desing) full HID USB core includes USB11T1A model) can
> > > directly be connected to usb D+ D- pins! (no tranceiver chip), there
> > > is some VB test program to talk to the core (as it is HID peripheral)
> > >
> > > antti
> > > PS I am afraid you have todo some homework cant do it for you

> >
> >

>
>



Reply With Quote
  #11 (permalink)  
Old 09-30-2003, 05:49 AM
Paul Leventis
Guest
 
Posts: n/a
Default Re: USB 1.1/2.0 Implementation

Hi,

Well, serves me right for going away... all my posts are for naught :-)

One small correction: DLLs are *not* PLLs -- though their first-order
behaviour seems similar. They are fundamentally different approaches to
solving the same problem. DLLs pass an input clock through a programmable
delay chain, and adjusts delay until the edges of the output clock and input
clock align. PLLs synthesize a clock via a VCO and phase shift the
resulting clock relative to the input clock. This means high-frequency
jitter on the input is filtered out in a PLL, but transmitted in a DLL.
PLLs usually have better clock frequency synthesis options, as they can
include multiply/divide counters in their feedback loop; DLLs can provide
some such capabilities via digital hardware, but it is very limited. There
are other differences between the two in how they respond to low- and
high-frequency jitter/drift, their noise susceptibility, range of operation
in input/output frequencies, granularity of phase/frequency adjustment,
response to temperature/voltage variation, and numerous other areas that I
can't recall precisely. Which is better depends on your application, though
generally speaking PLLs provide a more versatile solution.

Obviously we at Altera feel that PLLs are the better choice for our users,
as this is what we have chosen to build on all of our devices since APEX.
Stratix includes up to 12 PLLs of various flavours.

I can't help you on the device driver front.

I'll pass on your comes re: usb core availability and your experience with
the web to the appropriate groups.

Regards,

Paul Leventis
Altera Corp.


"SneakerNet" <[email protected]> wrote in message
news:[email protected]
> Hello again Paul ;o)
>
> LOL, tell you what, I already cracked it. I found that document sometime
> back now *grins*.
> And I also cracked that the CLKDLL is just a pll *grins again* and thus I
> had posted another msg (which you have already replied before) but once
> again I beat you to it. I cracked it before you replied ;o).
>
> Anyway thanks for taking time in explaning the Xilinx components.
> Regarding the free USB Cores from Altera website.
> Service I would give umm 10% *no offence*. I had to log into that page and
> request the core nearly 10 times before someone contacted me from Altera.
> Then after 2-3 days they told me that USB 2.0 core is not functional so i
> asked for usb 1.1 core. Then they asked me hundreds of questions of

why/what
> for/how long etc etc. When I finally got it, it was only licenced for a
> month (which passes by just like that as I'm working on this USB project
> part time.
> Anyway I found a site that had the full VHDL USB core free of cost

(without
> any need for any hardware). I'm stuck at the windows driver now. Rest is

all
> ready to go..
>
> Any help on how to install a generic usb driver?
>
> Thanks for your response Paul.
> Bye
>
> "Paul Leventis" <[email protected]> wrote in message
> news:[email protected] able.rogers.com...
> > Hi SneakerNet,
> >
> > I just noticed we have VERY handy application note for you -- AN307
> > (available on www.altera.com) describes how to migrate from a Xilinx

> design
> > to an Altera design. There is a section dedicated to DLL to PLL

> conversion
> > that should be able to help you out. Below is my attempt at explaining
> > things before I found this app note.
> >
> > In Altera's FPGAs, we've got PLLs, which provide a superset of the

CLKDLL
> > function you're trying to use. You'd want to setup your PLL to use

CLKIN
> as
> > its input inclk0, hook up the C0 port to GCLK signal and C1 port to CLK
> > signal, don't apply any phase shift, and use the C0 port to compensate

the
> > PLL output. Connect RST to the areset port, and LOCKED to the locked

> port.
> > You'll want to setup your C1 port to have a 2x frequency multiplier on

it.
> > The Lock and Reset signals have some sort of equivalent that I can't

> recall.
> > You can do this all through the allpll megafunction.
> >
> > The BUFGs are not necessary in Altera parts. In Xilinx parts, these

> buffers
> > are needed to explicitly indicate that you want a signal to be driven

onto
> > the global clock network. Quartus allows you to make "global"

assignments
> > to nets, but it automatically promotes anything it finds that looks like

a
> > clock net, as well as high-fanout or asynchronous signals if there are
> > enough global clocks available. The PLL output nets will be

automatically
> > promoted to global clock nets for you, and the PLL input will be

assigned
> to
> > the associated input clock pin.
> >
> > Also, I should point out that there are four USB cores listed on our
> > Intellectual Property page (www.altera.com) under Interfaces &

Peripherals
> > under USB. All are available for free trial under our OpenCore

evaluation
> > program.
> >
> > Regards,
> >
> > Paul Leventis
> > Altera Corp.
> >
> >
> > "SneakerNet" <[email protected]> wrote in message
> > news:[email protected]
> > > Hi Antti
> > > Thanks for the response.
> > > haha. I don't expect anyone to do work for me, othwersie I won't learn
> > > anything, but I wouldn't mind some guidance along the way from you

> guys..
> > > Anyway I need to ask 2 questions regarding your reply.
> > > 1. When you say USB11T11A, do you mean the Philips tranceiver

> PDIUSBP11A?
> > If
> > > no then I'm sorry but i'm not able to find anything on USB11T11A. Have

I
> > > gone blind?
> > > 2. Regarding the usb (japanese design), I have ended up towards a

brick
> > > wall. What I mean to say is, I have been looking at the design for

> couple
> > of
> > > hours and there are 4 components that I'm not sure what they do. The

> main
> > > problem is that the code was written for a Xilinx component and

because
> > I'm
> > > using Altera component, I'm do not have the librabires that these

> > component
> > > are using.
> > > Firstly the library defined is (which is for Xilinx only (pls correct

me
> > if
> > > i'm wrong))
> > > library unisim;
> > > use unisim.vcomponents.all;
> > >
> > > and the 4 components that are using this library are
> > > u_DLL : CLKDLL
> > > port map ( CLKIN => CLKINM,
> > > CLKFB => GCLK,
> > > RST => RST,
> > > CLK0 => GCLKM,
> > > CLK2X => CLKM,
> > > LOCKED => LOCK
> > > );
> > >
> > > u_GCLK : BUFG
> > > port map ( I => GCLKM,
> > > O => GCLK
> > > );
> > >
> > > u_CLK : BUFG
> > > port map ( I => CLKM,
> > > O => CLK
> > > );
> > >
> > > u_CLKIN : IBUFG
> > > port map ( I => CLKIN,
> > > O => CLKINM
> > > );
> > >
> > > If you can explain me how I can replace these components for Altera

> > design,
> > > I will have a step to progress. If I can get past this point, then I

> have
> > > something to try on the chip and play around. My problem is that right

> now
> > I
> > > can't go past compiling as Quartus doesn't recognize these components

> (or
> > > the library). Pls Advice
> > >
> > > Thanks again
> > >
> > > Regards
> > >
> > >
> > > "Antti Lukats" <[email protected]> wrote in message
> > > news:[email protected] om...
> > > > "SneakerNet" <[email protected]> wrote in message news:<p43cb.157047
> > > > > Has anyone successfully implemented USB 2.0 or USB 1.1 protocol in
> > > > [deleted]
> > > >
> > > > USB11T11A FS/LS USB tranceiver
> > > >
> > > > usb_phy (opencores) UTMI interface that connects to USB11T11A
> > > >
> > > > usb1.1 (opencores) connects to usb_phy (opencores) connects to
> > > > USB11T1A it is not HID but it will enumerate in hardware iw the USB
> > > > host will 'see' it, but ther is no host software provide
> > > >
> > > > usb (japanase desing) full HID USB core includes USB11T1A model) can
> > > > directly be connected to usb D+ D- pins! (no tranceiver chip), there
> > > > is some VB test program to talk to the core (as it is HID

peripheral)
> > > >
> > > > antti
> > > > PS I am afraid you have todo some homework cant do it for you
> > >
> > >

> >
> >

>
>



Reply With Quote
  #12 (permalink)  
Old 09-30-2003, 07:59 PM
Ken Land
Guest
 
Posts: n/a
Default Re: USB 1.1/2.0 Implementation

Hey Sneaker,

I can't give you the code to our host side driver (I don't own it) but I can
tell you its a slight modification to a sample driver in the MicroSoft
Device Driver Kit.

From the original header. (So you could search)

Copyright (c) 1995 Microsoft Corporation
Module Name:
I82930.c
Abstract:
USB device driver for Intel 82930 USB test board
Environment:
kernel mode only

So if you have access to or can get the MS DDK then I think it has all you
need.
Our setup was pretty much done for us, but you need to compile this driver
with a unique filename and maybe your USB ID (not sure about this) and then
you setup a .inf file that says your device uses this driver file.
(executable renamed to SneakersUSB.SYS or such)

"your device" is the name that should show up even without a driver when you
plug it into a Windows box. I assume the USB core has some default. (.inf
file basically maps this name to which driver to load. May be able to use
someone elses driver by creating a .inf for all I know)

Surprised they gave away the core, but not the driver they tested it with.

Good Luck!
Ken




"SneakerNet" <[email protected]> wrote in message
news:[email protected]
> Hello again Paul ;o)
>
> LOL, tell you what, I already cracked it. I found that document sometime
> back now *grins*.
> And I also cracked that the CLKDLL is just a pll *grins again* and thus I
> had posted another msg (which you have already replied before) but once
> again I beat you to it. I cracked it before you replied ;o).
>
> Anyway thanks for taking time in explaning the Xilinx components.
> Regarding the free USB Cores from Altera website.
> Service I would give umm 10% *no offence*. I had to log into that page and
> request the core nearly 10 times before someone contacted me from Altera.
> Then after 2-3 days they told me that USB 2.0 core is not functional so i
> asked for usb 1.1 core. Then they asked me hundreds of questions of

why/what
> for/how long etc etc. When I finally got it, it was only licenced for a
> month (which passes by just like that as I'm working on this USB project
> part time.
> Anyway I found a site that had the full VHDL USB core free of cost

(without
> any need for any hardware). I'm stuck at the windows driver now. Rest is

all
> ready to go..
>
> Any help on how to install a generic usb driver?
>
> Thanks for your response Paul.
> Bye
>
> "Paul Leventis" <[email protected]> wrote in message
> news:[email protected] able.rogers.com...
> > Hi SneakerNet,
> >
> > I just noticed we have VERY handy application note for you -- AN307
> > (available on www.altera.com) describes how to migrate from a Xilinx

> design
> > to an Altera design. There is a section dedicated to DLL to PLL

> conversion
> > that should be able to help you out. Below is my attempt at explaining
> > things before I found this app note.
> >
> > In Altera's FPGAs, we've got PLLs, which provide a superset of the

CLKDLL
> > function you're trying to use. You'd want to setup your PLL to use

CLKIN
> as
> > its input inclk0, hook up the C0 port to GCLK signal and C1 port to CLK
> > signal, don't apply any phase shift, and use the C0 port to compensate

the
> > PLL output. Connect RST to the areset port, and LOCKED to the locked

> port.
> > You'll want to setup your C1 port to have a 2x frequency multiplier on

it.
> > The Lock and Reset signals have some sort of equivalent that I can't

> recall.
> > You can do this all through the allpll megafunction.
> >
> > The BUFGs are not necessary in Altera parts. In Xilinx parts, these

> buffers
> > are needed to explicitly indicate that you want a signal to be driven

onto
> > the global clock network. Quartus allows you to make "global"

assignments
> > to nets, but it automatically promotes anything it finds that looks like

a
> > clock net, as well as high-fanout or asynchronous signals if there are
> > enough global clocks available. The PLL output nets will be

automatically
> > promoted to global clock nets for you, and the PLL input will be

assigned
> to
> > the associated input clock pin.
> >
> > Also, I should point out that there are four USB cores listed on our
> > Intellectual Property page (www.altera.com) under Interfaces &

Peripherals
> > under USB. All are available for free trial under our OpenCore

evaluation
> > program.
> >
> > Regards,
> >
> > Paul Leventis
> > Altera Corp.
> >
> >
> > "SneakerNet" <[email protected]> wrote in message
> > news:[email protected]
> > > Hi Antti
> > > Thanks for the response.
> > > haha. I don't expect anyone to do work for me, othwersie I won't learn
> > > anything, but I wouldn't mind some guidance along the way from you

> guys..
> > > Anyway I need to ask 2 questions regarding your reply.
> > > 1. When you say USB11T11A, do you mean the Philips tranceiver

> PDIUSBP11A?
> > If
> > > no then I'm sorry but i'm not able to find anything on USB11T11A. Have

I
> > > gone blind?
> > > 2. Regarding the usb (japanese design), I have ended up towards a

brick
> > > wall. What I mean to say is, I have been looking at the design for

> couple
> > of
> > > hours and there are 4 components that I'm not sure what they do. The

> main
> > > problem is that the code was written for a Xilinx component and

because
> > I'm
> > > using Altera component, I'm do not have the librabires that these

> > component
> > > are using.
> > > Firstly the library defined is (which is for Xilinx only (pls correct

me
> > if
> > > i'm wrong))
> > > library unisim;
> > > use unisim.vcomponents.all;
> > >
> > > and the 4 components that are using this library are
> > > u_DLL : CLKDLL
> > > port map ( CLKIN => CLKINM,
> > > CLKFB => GCLK,
> > > RST => RST,
> > > CLK0 => GCLKM,
> > > CLK2X => CLKM,
> > > LOCKED => LOCK
> > > );
> > >
> > > u_GCLK : BUFG
> > > port map ( I => GCLKM,
> > > O => GCLK
> > > );
> > >
> > > u_CLK : BUFG
> > > port map ( I => CLKM,
> > > O => CLK
> > > );
> > >
> > > u_CLKIN : IBUFG
> > > port map ( I => CLKIN,
> > > O => CLKINM
> > > );
> > >
> > > If you can explain me how I can replace these components for Altera

> > design,
> > > I will have a step to progress. If I can get past this point, then I

> have
> > > something to try on the chip and play around. My problem is that right

> now
> > I
> > > can't go past compiling as Quartus doesn't recognize these components

> (or
> > > the library). Pls Advice
> > >
> > > Thanks again
> > >
> > > Regards
> > >
> > >
> > > "Antti Lukats" <[email protected]> wrote in message
> > > news:[email protected] om...
> > > > "SneakerNet" <[email protected]> wrote in message news:<p43cb.157047
> > > > > Has anyone successfully implemented USB 2.0 or USB 1.1 protocol in
> > > > [deleted]
> > > >
> > > > USB11T11A FS/LS USB tranceiver
> > > >
> > > > usb_phy (opencores) UTMI interface that connects to USB11T11A
> > > >
> > > > usb1.1 (opencores) connects to usb_phy (opencores) connects to
> > > > USB11T1A it is not HID but it will enumerate in hardware iw the USB
> > > > host will 'see' it, but ther is no host software provide
> > > >
> > > > usb (japanase desing) full HID USB core includes USB11T1A model) can
> > > > directly be connected to usb D+ D- pins! (no tranceiver chip), there
> > > > is some VB test program to talk to the core (as it is HID

peripheral)
> > > >
> > > > antti
> > > > PS I am afraid you have todo some homework cant do it for you
> > >
> > >

> >
> >

>
>



Reply With Quote
  #13 (permalink)  
Old 09-30-2003, 09:59 PM
SneakerNet
Guest
 
Posts: n/a
Default Re: USB 1.1/2.0 Implementation

Hi Ken

Thanks for the important tip. I'll give that a shot. (so there is no way u
can send me driver? all i need is a driver with vendor id = 0c91 and product
id = 2001).
Anyway like u mentioned, very big pity that the guys didn't include drivers
and they gave their whole vhdl code free. Pity!

Hope god has mercy on my soul while i'm doing usb driver.. LOL
Thanks Ken
Kind Regards



"Ken Land" <[email protected]> wrote in message
news:[email protected]
> Hey Sneaker,
>
> I can't give you the code to our host side driver (I don't own it) but I

can
> tell you its a slight modification to a sample driver in the MicroSoft
> Device Driver Kit.
>
> From the original header. (So you could search)
>
> Copyright (c) 1995 Microsoft Corporation
> Module Name:
> I82930.c
> Abstract:
> USB device driver for Intel 82930 USB test board
> Environment:
> kernel mode only
>
> So if you have access to or can get the MS DDK then I think it has all you
> need.
> Our setup was pretty much done for us, but you need to compile this driver
> with a unique filename and maybe your USB ID (not sure about this) and

then
> you setup a .inf file that says your device uses this driver file.
> (executable renamed to SneakersUSB.SYS or such)
>
> "your device" is the name that should show up even without a driver when

you
> plug it into a Windows box. I assume the USB core has some default. (.inf
> file basically maps this name to which driver to load. May be able to use
> someone elses driver by creating a .inf for all I know)
>
> Surprised they gave away the core, but not the driver they tested it with.
>
> Good Luck!
> Ken
>
>
>
>
> "SneakerNet" <[email protected]> wrote in message
> news:[email protected]
> > Hello again Paul ;o)
> >
> > LOL, tell you what, I already cracked it. I found that document sometime
> > back now *grins*.
> > And I also cracked that the CLKDLL is just a pll *grins again* and thus

I
> > had posted another msg (which you have already replied before) but once
> > again I beat you to it. I cracked it before you replied ;o).
> >
> > Anyway thanks for taking time in explaning the Xilinx components.
> > Regarding the free USB Cores from Altera website.
> > Service I would give umm 10% *no offence*. I had to log into that page

and
> > request the core nearly 10 times before someone contacted me from

Altera.
> > Then after 2-3 days they told me that USB 2.0 core is not functional so

i
> > asked for usb 1.1 core. Then they asked me hundreds of questions of

> why/what
> > for/how long etc etc. When I finally got it, it was only licenced for a
> > month (which passes by just like that as I'm working on this USB project
> > part time.
> > Anyway I found a site that had the full VHDL USB core free of cost

> (without
> > any need for any hardware). I'm stuck at the windows driver now. Rest is

> all
> > ready to go..
> >
> > Any help on how to install a generic usb driver?
> >
> > Thanks for your response Paul.
> > Bye
> >
> > "Paul Leventis" <[email protected]> wrote in message
> > news:[email protected] able.rogers.com...
> > > Hi SneakerNet,
> > >
> > > I just noticed we have VERY handy application note for you -- AN307
> > > (available on www.altera.com) describes how to migrate from a Xilinx

> > design
> > > to an Altera design. There is a section dedicated to DLL to PLL

> > conversion
> > > that should be able to help you out. Below is my attempt at

explaining
> > > things before I found this app note.
> > >
> > > In Altera's FPGAs, we've got PLLs, which provide a superset of the

> CLKDLL
> > > function you're trying to use. You'd want to setup your PLL to use

> CLKIN
> > as
> > > its input inclk0, hook up the C0 port to GCLK signal and C1 port to

CLK
> > > signal, don't apply any phase shift, and use the C0 port to compensate

> the
> > > PLL output. Connect RST to the areset port, and LOCKED to the locked

> > port.
> > > You'll want to setup your C1 port to have a 2x frequency multiplier on

> it.
> > > The Lock and Reset signals have some sort of equivalent that I can't

> > recall.
> > > You can do this all through the allpll megafunction.
> > >
> > > The BUFGs are not necessary in Altera parts. In Xilinx parts, these

> > buffers
> > > are needed to explicitly indicate that you want a signal to be driven

> onto
> > > the global clock network. Quartus allows you to make "global"

> assignments
> > > to nets, but it automatically promotes anything it finds that looks

like
> a
> > > clock net, as well as high-fanout or asynchronous signals if there are
> > > enough global clocks available. The PLL output nets will be

> automatically
> > > promoted to global clock nets for you, and the PLL input will be

> assigned
> > to
> > > the associated input clock pin.
> > >
> > > Also, I should point out that there are four USB cores listed on our
> > > Intellectual Property page (www.altera.com) under Interfaces &

> Peripherals
> > > under USB. All are available for free trial under our OpenCore

> evaluation
> > > program.
> > >
> > > Regards,
> > >
> > > Paul Leventis
> > > Altera Corp.
> > >
> > >
> > > "SneakerNet" <[email protected]> wrote in message
> > > news:[email protected]
> > > > Hi Antti
> > > > Thanks for the response.
> > > > haha. I don't expect anyone to do work for me, othwersie I won't

learn
> > > > anything, but I wouldn't mind some guidance along the way from you

> > guys..
> > > > Anyway I need to ask 2 questions regarding your reply.
> > > > 1. When you say USB11T11A, do you mean the Philips tranceiver

> > PDIUSBP11A?
> > > If
> > > > no then I'm sorry but i'm not able to find anything on USB11T11A.

Have
> I
> > > > gone blind?
> > > > 2. Regarding the usb (japanese design), I have ended up towards a

> brick
> > > > wall. What I mean to say is, I have been looking at the design for

> > couple
> > > of
> > > > hours and there are 4 components that I'm not sure what they do. The

> > main
> > > > problem is that the code was written for a Xilinx component and

> because
> > > I'm
> > > > using Altera component, I'm do not have the librabires that these
> > > component
> > > > are using.
> > > > Firstly the library defined is (which is for Xilinx only (pls

correct
> me
> > > if
> > > > i'm wrong))
> > > > library unisim;
> > > > use unisim.vcomponents.all;
> > > >
> > > > and the 4 components that are using this library are
> > > > u_DLL : CLKDLL
> > > > port map ( CLKIN => CLKINM,
> > > > CLKFB => GCLK,
> > > > RST => RST,
> > > > CLK0 => GCLKM,
> > > > CLK2X => CLKM,
> > > > LOCKED => LOCK
> > > > );
> > > >
> > > > u_GCLK : BUFG
> > > > port map ( I => GCLKM,
> > > > O => GCLK
> > > > );
> > > >
> > > > u_CLK : BUFG
> > > > port map ( I => CLKM,
> > > > O => CLK
> > > > );
> > > >
> > > > u_CLKIN : IBUFG
> > > > port map ( I => CLKIN,
> > > > O => CLKINM
> > > > );
> > > >
> > > > If you can explain me how I can replace these components for Altera
> > > design,
> > > > I will have a step to progress. If I can get past this point, then I

> > have
> > > > something to try on the chip and play around. My problem is that

right
> > now
> > > I
> > > > can't go past compiling as Quartus doesn't recognize these

components
> > (or
> > > > the library). Pls Advice
> > > >
> > > > Thanks again
> > > >
> > > > Regards
> > > >
> > > >
> > > > "Antti Lukats" <[email protected]> wrote in message
> > > > news:[email protected] om...
> > > > > "SneakerNet" <[email protected]> wrote in message

news:<p43cb.157047
> > > > > > Has anyone successfully implemented USB 2.0 or USB 1.1 protocol

in
> > > > > [deleted]
> > > > >
> > > > > USB11T11A FS/LS USB tranceiver
> > > > >
> > > > > usb_phy (opencores) UTMI interface that connects to USB11T11A
> > > > >
> > > > > usb1.1 (opencores) connects to usb_phy (opencores) connects to
> > > > > USB11T1A it is not HID but it will enumerate in hardware iw the

USB
> > > > > host will 'see' it, but ther is no host software provide
> > > > >
> > > > > usb (japanase desing) full HID USB core includes USB11T1A model)

can
> > > > > directly be connected to usb D+ D- pins! (no tranceiver chip),

there
> > > > > is some VB test program to talk to the core (as it is HID

> peripheral)
> > > > >
> > > > > antti
> > > > > PS I am afraid you have todo some homework cant do it for you
> > > >
> > > >
> > >
> > >

> >
> >

>
>



Reply With Quote
  #14 (permalink)  
Old 09-30-2003, 10:25 PM
SneakerNet
Guest
 
Posts: n/a
Default Re: USB 1.1/2.0 Implementation

LOL
Thanks Paul
All help appreciated at this stage..

"Paul Leventis" <[email protected]> wrote in message
news[email protected] ble.rogers.com...
> Hi,
>
> Well, serves me right for going away... all my posts are for naught :-)
>
> One small correction: DLLs are *not* PLLs -- though their first-order
> behaviour seems similar. They are fundamentally different approaches to
> solving the same problem. DLLs pass an input clock through a programmable
> delay chain, and adjusts delay until the edges of the output clock and

input
> clock align. PLLs synthesize a clock via a VCO and phase shift the
> resulting clock relative to the input clock. This means high-frequency
> jitter on the input is filtered out in a PLL, but transmitted in a DLL.
> PLLs usually have better clock frequency synthesis options, as they can
> include multiply/divide counters in their feedback loop; DLLs can provide
> some such capabilities via digital hardware, but it is very limited.

There
> are other differences between the two in how they respond to low- and
> high-frequency jitter/drift, their noise susceptibility, range of

operation
> in input/output frequencies, granularity of phase/frequency adjustment,
> response to temperature/voltage variation, and numerous other areas that I
> can't recall precisely. Which is better depends on your application,

though
> generally speaking PLLs provide a more versatile solution.
>
> Obviously we at Altera feel that PLLs are the better choice for our users,
> as this is what we have chosen to build on all of our devices since APEX.
> Stratix includes up to 12 PLLs of various flavours.
>
> I can't help you on the device driver front.
>
> I'll pass on your comes re: usb core availability and your experience with
> the web to the appropriate groups.
>
> Regards,
>
> Paul Leventis
> Altera Corp.
>
>
> "SneakerNet" <[email protected]> wrote in message
> news:[email protected]
> > Hello again Paul ;o)
> >
> > LOL, tell you what, I already cracked it. I found that document sometime
> > back now *grins*.
> > And I also cracked that the CLKDLL is just a pll *grins again* and thus

I
> > had posted another msg (which you have already replied before) but once
> > again I beat you to it. I cracked it before you replied ;o).
> >
> > Anyway thanks for taking time in explaning the Xilinx components.
> > Regarding the free USB Cores from Altera website.
> > Service I would give umm 10% *no offence*. I had to log into that page

and
> > request the core nearly 10 times before someone contacted me from

Altera.
> > Then after 2-3 days they told me that USB 2.0 core is not functional so

i
> > asked for usb 1.1 core. Then they asked me hundreds of questions of

> why/what
> > for/how long etc etc. When I finally got it, it was only licenced for a
> > month (which passes by just like that as I'm working on this USB project
> > part time.
> > Anyway I found a site that had the full VHDL USB core free of cost

> (without
> > any need for any hardware). I'm stuck at the windows driver now. Rest is

> all
> > ready to go..
> >
> > Any help on how to install a generic usb driver?
> >
> > Thanks for your response Paul.
> > Bye
> >
> > "Paul Leventis" <[email protected]> wrote in message
> > news:[email protected] able.rogers.com...
> > > Hi SneakerNet,
> > >
> > > I just noticed we have VERY handy application note for you -- AN307
> > > (available on www.altera.com) describes how to migrate from a Xilinx

> > design
> > > to an Altera design. There is a section dedicated to DLL to PLL

> > conversion
> > > that should be able to help you out. Below is my attempt at

explaining
> > > things before I found this app note.
> > >
> > > In Altera's FPGAs, we've got PLLs, which provide a superset of the

> CLKDLL
> > > function you're trying to use. You'd want to setup your PLL to use

> CLKIN
> > as
> > > its input inclk0, hook up the C0 port to GCLK signal and C1 port to

CLK
> > > signal, don't apply any phase shift, and use the C0 port to compensate

> the
> > > PLL output. Connect RST to the areset port, and LOCKED to the locked

> > port.
> > > You'll want to setup your C1 port to have a 2x frequency multiplier on

> it.
> > > The Lock and Reset signals have some sort of equivalent that I can't

> > recall.
> > > You can do this all through the allpll megafunction.
> > >
> > > The BUFGs are not necessary in Altera parts. In Xilinx parts, these

> > buffers
> > > are needed to explicitly indicate that you want a signal to be driven

> onto
> > > the global clock network. Quartus allows you to make "global"

> assignments
> > > to nets, but it automatically promotes anything it finds that looks

like
> a
> > > clock net, as well as high-fanout or asynchronous signals if there are
> > > enough global clocks available. The PLL output nets will be

> automatically
> > > promoted to global clock nets for you, and the PLL input will be

> assigned
> > to
> > > the associated input clock pin.
> > >
> > > Also, I should point out that there are four USB cores listed on our
> > > Intellectual Property page (www.altera.com) under Interfaces &

> Peripherals
> > > under USB. All are available for free trial under our OpenCore

> evaluation
> > > program.
> > >
> > > Regards,
> > >
> > > Paul Leventis
> > > Altera Corp.
> > >
> > >
> > > "SneakerNet" <[email protected]> wrote in message
> > > news:[email protected]
> > > > Hi Antti
> > > > Thanks for the response.
> > > > haha. I don't expect anyone to do work for me, othwersie I won't

learn
> > > > anything, but I wouldn't mind some guidance along the way from you

> > guys..
> > > > Anyway I need to ask 2 questions regarding your reply.
> > > > 1. When you say USB11T11A, do you mean the Philips tranceiver

> > PDIUSBP11A?
> > > If
> > > > no then I'm sorry but i'm not able to find anything on USB11T11A.

Have
> I
> > > > gone blind?
> > > > 2. Regarding the usb (japanese design), I have ended up towards a

> brick
> > > > wall. What I mean to say is, I have been looking at the design for

> > couple
> > > of
> > > > hours and there are 4 components that I'm not sure what they do. The

> > main
> > > > problem is that the code was written for a Xilinx component and

> because
> > > I'm
> > > > using Altera component, I'm do not have the librabires that these
> > > component
> > > > are using.
> > > > Firstly the library defined is (which is for Xilinx only (pls

correct
> me
> > > if
> > > > i'm wrong))
> > > > library unisim;
> > > > use unisim.vcomponents.all;
> > > >
> > > > and the 4 components that are using this library are
> > > > u_DLL : CLKDLL
> > > > port map ( CLKIN => CLKINM,
> > > > CLKFB => GCLK,
> > > > RST => RST,
> > > > CLK0 => GCLKM,
> > > > CLK2X => CLKM,
> > > > LOCKED => LOCK
> > > > );
> > > >
> > > > u_GCLK : BUFG
> > > > port map ( I => GCLKM,
> > > > O => GCLK
> > > > );
> > > >
> > > > u_CLK : BUFG
> > > > port map ( I => CLKM,
> > > > O => CLK
> > > > );
> > > >
> > > > u_CLKIN : IBUFG
> > > > port map ( I => CLKIN,
> > > > O => CLKINM
> > > > );
> > > >
> > > > If you can explain me how I can replace these components for Altera
> > > design,
> > > > I will have a step to progress. If I can get past this point, then I

> > have
> > > > something to try on the chip and play around. My problem is that

right
> > now
> > > I
> > > > can't go past compiling as Quartus doesn't recognize these

components
> > (or
> > > > the library). Pls Advice
> > > >
> > > > Thanks again
> > > >
> > > > Regards
> > > >
> > > >
> > > > "Antti Lukats" <[email protected]> wrote in message
> > > > news:[email protected] om...
> > > > > "SneakerNet" <[email protected]> wrote in message

news:<p43cb.157047
> > > > > > Has anyone successfully implemented USB 2.0 or USB 1.1 protocol

in
> > > > > [deleted]
> > > > >
> > > > > USB11T11A FS/LS USB tranceiver
> > > > >
> > > > > usb_phy (opencores) UTMI interface that connects to USB11T11A
> > > > >
> > > > > usb1.1 (opencores) connects to usb_phy (opencores) connects to
> > > > > USB11T1A it is not HID but it will enumerate in hardware iw the

USB
> > > > > host will 'see' it, but ther is no host software provide
> > > > >
> > > > > usb (japanase desing) full HID USB core includes USB11T1A model)

can
> > > > > directly be connected to usb D+ D- pins! (no tranceiver chip),

there
> > > > > is some VB test program to talk to the core (as it is HID

> peripheral)
> > > > >
> > > > > antti
> > > > > PS I am afraid you have todo some homework cant do it for you
> > > >
> > > >
> > >
> > >

> >
> >

>
>



Reply With Quote
  #15 (permalink)  
Old 10-01-2003, 01:22 AM
Kenneth Land
Guest
 
Posts: n/a
Default Re: USB 1.1/2.0 Implementation


So, when you plugin your device, does Windows say New Device Found, etc.?
Giving you a chance to install a driver? If so, does it tell you the name
of the device?

I"ve never built our driver, but I'll give it the ol' 15 minute try.

Ken

"SneakerNet" <[email protected]> wrote in message
news:[email protected]
> Hi Ken
>
> Thanks for the important tip. I'll give that a shot. (so there is no way u
> can send me driver? all i need is a driver with vendor id = 0c91 and

product
> id = 2001).
> Anyway like u mentioned, very big pity that the guys didn't include

drivers
> and they gave their whole vhdl code free. Pity!
>
> Hope god has mercy on my soul while i'm doing usb driver.. LOL
> Thanks Ken
> Kind Regards
>
>
>
> "Ken Land" <[email protected]> wrote in message
> news:[email protected]
> > Hey Sneaker,
> >
> > I can't give you the code to our host side driver (I don't own it) but I

> can
> > tell you its a slight modification to a sample driver in the MicroSoft
> > Device Driver Kit.
> >
> > From the original header. (So you could search)
> >
> > Copyright (c) 1995 Microsoft Corporation
> > Module Name:
> > I82930.c
> > Abstract:
> > USB device driver for Intel 82930 USB test board
> > Environment:
> > kernel mode only
> >
> > So if you have access to or can get the MS DDK then I think it has all

you
> > need.
> > Our setup was pretty much done for us, but you need to compile this

driver
> > with a unique filename and maybe your USB ID (not sure about this) and

> then
> > you setup a .inf file that says your device uses this driver file.
> > (executable renamed to SneakersUSB.SYS or such)
> >
> > "your device" is the name that should show up even without a driver when

> you
> > plug it into a Windows box. I assume the USB core has some default.

(.inf
> > file basically maps this name to which driver to load. May be able to

use
> > someone elses driver by creating a .inf for all I know)
> >
> > Surprised they gave away the core, but not the driver they tested it

with.
> >
> > Good Luck!
> > Ken
> >
> >
> >
> >
> > "SneakerNet" <[email protected]> wrote in message
> > news:[email protected]
> > > Hello again Paul ;o)
> > >
> > > LOL, tell you what, I already cracked it. I found that document

sometime
> > > back now *grins*.
> > > And I also cracked that the CLKDLL is just a pll *grins again* and

thus
> I
> > > had posted another msg (which you have already replied before) but

once
> > > again I beat you to it. I cracked it before you replied ;o).
> > >
> > > Anyway thanks for taking time in explaning the Xilinx components.
> > > Regarding the free USB Cores from Altera website.
> > > Service I would give umm 10% *no offence*. I had to log into that page

> and
> > > request the core nearly 10 times before someone contacted me from

> Altera.
> > > Then after 2-3 days they told me that USB 2.0 core is not functional

so
> i
> > > asked for usb 1.1 core. Then they asked me hundreds of questions of

> > why/what
> > > for/how long etc etc. When I finally got it, it was only licenced for

a
> > > month (which passes by just like that as I'm working on this USB

project
> > > part time.
> > > Anyway I found a site that had the full VHDL USB core free of cost

> > (without
> > > any need for any hardware). I'm stuck at the windows driver now. Rest

is
> > all
> > > ready to go..
> > >
> > > Any help on how to install a generic usb driver?
> > >
> > > Thanks for your response Paul.
> > > Bye
> > >
> > > "Paul Leventis" <[email protected]> wrote in message
> > > news:[email protected] able.rogers.com...
> > > > Hi SneakerNet,
> > > >
> > > > I just noticed we have VERY handy application note for you -- AN307
> > > > (available on www.altera.com) describes how to migrate from a Xilinx
> > > design
> > > > to an Altera design. There is a section dedicated to DLL to PLL
> > > conversion
> > > > that should be able to help you out. Below is my attempt at

> explaining
> > > > things before I found this app note.
> > > >
> > > > In Altera's FPGAs, we've got PLLs, which provide a superset of the

> > CLKDLL
> > > > function you're trying to use. You'd want to setup your PLL to use

> > CLKIN
> > > as
> > > > its input inclk0, hook up the C0 port to GCLK signal and C1 port to

> CLK
> > > > signal, don't apply any phase shift, and use the C0 port to

compensate
> > the
> > > > PLL output. Connect RST to the areset port, and LOCKED to the

locked
> > > port.
> > > > You'll want to setup your C1 port to have a 2x frequency multiplier

on
> > it.
> > > > The Lock and Reset signals have some sort of equivalent that I can't
> > > recall.
> > > > You can do this all through the allpll megafunction.
> > > >
> > > > The BUFGs are not necessary in Altera parts. In Xilinx parts, these
> > > buffers
> > > > are needed to explicitly indicate that you want a signal to be

driven
> > onto
> > > > the global clock network. Quartus allows you to make "global"

> > assignments
> > > > to nets, but it automatically promotes anything it finds that looks

> like
> > a
> > > > clock net, as well as high-fanout or asynchronous signals if there

are
> > > > enough global clocks available. The PLL output nets will be

> > automatically
> > > > promoted to global clock nets for you, and the PLL input will be

> > assigned
> > > to
> > > > the associated input clock pin.
> > > >
> > > > Also, I should point out that there are four USB cores listed on our
> > > > Intellectual Property page (www.altera.com) under Interfaces &

> > Peripherals
> > > > under USB. All are available for free trial under our OpenCore

> > evaluation
> > > > program.
> > > >
> > > > Regards,
> > > >
> > > > Paul Leventis
> > > > Altera Corp.
> > > >
> > > >
> > > > "SneakerNet" <[email protected]> wrote in message
> > > > news:[email protected]
> > > > > Hi Antti
> > > > > Thanks for the response.
> > > > > haha. I don't expect anyone to do work for me, othwersie I won't

> learn
> > > > > anything, but I wouldn't mind some guidance along the way from you
> > > guys..
> > > > > Anyway I need to ask 2 questions regarding your reply.
> > > > > 1. When you say USB11T11A, do you mean the Philips tranceiver
> > > PDIUSBP11A?
> > > > If
> > > > > no then I'm sorry but i'm not able to find anything on USB11T11A.

> Have
> > I
> > > > > gone blind?
> > > > > 2. Regarding the usb (japanese design), I have ended up towards a

> > brick
> > > > > wall. What I mean to say is, I have been looking at the design for
> > > couple
> > > > of
> > > > > hours and there are 4 components that I'm not sure what they do.

The
> > > main
> > > > > problem is that the code was written for a Xilinx component and

> > because
> > > > I'm
> > > > > using Altera component, I'm do not have the librabires that these
> > > > component
> > > > > are using.
> > > > > Firstly the library defined is (which is for Xilinx only (pls

> correct
> > me
> > > > if
> > > > > i'm wrong))
> > > > > library unisim;
> > > > > use unisim.vcomponents.all;
> > > > >
> > > > > and the 4 components that are using this library are
> > > > > u_DLL : CLKDLL
> > > > > port map ( CLKIN => CLKINM,
> > > > > CLKFB => GCLK,
> > > > > RST => RST,
> > > > > CLK0 => GCLKM,
> > > > > CLK2X => CLKM,
> > > > > LOCKED => LOCK
> > > > > );
> > > > >
> > > > > u_GCLK : BUFG
> > > > > port map ( I => GCLKM,
> > > > > O => GCLK
> > > > > );
> > > > >
> > > > > u_CLK : BUFG
> > > > > port map ( I => CLKM,
> > > > > O => CLK
> > > > > );
> > > > >
> > > > > u_CLKIN : IBUFG
> > > > > port map ( I => CLKIN,
> > > > > O => CLKINM
> > > > > );
> > > > >
> > > > > If you can explain me how I can replace these components for

Altera
> > > > design,
> > > > > I will have a step to progress. If I can get past this point, then

I
> > > have
> > > > > something to try on the chip and play around. My problem is that

> right
> > > now
> > > > I
> > > > > can't go past compiling as Quartus doesn't recognize these

> components
> > > (or
> > > > > the library). Pls Advice
> > > > >
> > > > > Thanks again
> > > > >
> > > > > Regards
> > > > >
> > > > >
> > > > > "Antti Lukats" <[email protected]> wrote in message
> > > > > news:[email protected] om...
> > > > > > "SneakerNet" <[email protected]> wrote in message

> news:<p43cb.157047
> > > > > > > Has anyone successfully implemented USB 2.0 or USB 1.1

protocol
> in
> > > > > > [deleted]
> > > > > >
> > > > > > USB11T11A FS/LS USB tranceiver
> > > > > >
> > > > > > usb_phy (opencores) UTMI interface that connects to USB11T11A
> > > > > >
> > > > > > usb1.1 (opencores) connects to usb_phy (opencores) connects to
> > > > > > USB11T1A it is not HID but it will enumerate in hardware iw the

> USB
> > > > > > host will 'see' it, but ther is no host software provide
> > > > > >
> > > > > > usb (japanase desing) full HID USB core includes USB11T1A model)

> can
> > > > > > directly be connected to usb D+ D- pins! (no tranceiver chip),

> there
> > > > > > is some VB test program to talk to the core (as it is HID

> > peripheral)
> > > > > >
> > > > > > antti
> > > > > > PS I am afraid you have todo some homework cant do it for you
> > > > >
> > > > >
> > > >
> > > >
> > >
> > >

> >
> >

>
>



Reply With Quote
  #16 (permalink)  
Old 10-01-2003, 02:06 AM
SneakerNet
Guest
 
Posts: n/a
Default Re: USB 1.1/2.0 Implementation

Hi Ken
Ok when i plug in the cable, windows reports a usb device is found, but
because win doesn' know what it is, it fails. I have attached a screenshot
(Sample.jpg, sorry about the attachment but I don't have web space to upload
on a site).

Now someone also mentioned to use Jongo WinDriver which I'm trying to use
it.
Firstly have u used this program your self. If you haven't used it then
reject the next line.
Secondly, this program allows you to generate a custom inf file (with
product and vendor id), which I do but when it comes to installing the new
custom driver, win2k doesn't like it and instead uses the
c:\winnt\inf\usb.inf file. This sucks.


Do you know what 'multi-interface device' means?
Cheers Ken
Regards

"Kenneth Land" <[email protected]> wrote in message
news:[email protected]
>
> So, when you plugin your device, does Windows say New Device Found, etc.?
> Giving you a chance to install a driver? If so, does it tell you the name
> of the device?
>
> I"ve never built our driver, but I'll give it the ol' 15 minute try.
>
> Ken
>
> "SneakerNet" <[email protected]> wrote in message
> news:[email protected]
> > Hi Ken
> >
> > Thanks for the important tip. I'll give that a shot. (so there is no way

u
> > can send me driver? all i need is a driver with vendor id = 0c91 and

> product
> > id = 2001).
> > Anyway like u mentioned, very big pity that the guys didn't include

> drivers
> > and they gave their whole vhdl code free. Pity!
> >
> > Hope god has mercy on my soul while i'm doing usb driver.. LOL
> > Thanks Ken
> > Kind Regards
> >
> >
> >
> > "Ken Land" <[email protected]> wrote in message
> > news:[email protected]
> > > Hey Sneaker,
> > >
> > > I can't give you the code to our host side driver (I don't own it) but

I
> > can
> > > tell you its a slight modification to a sample driver in the MicroSoft
> > > Device Driver Kit.
> > >
> > > From the original header. (So you could search)
> > >
> > > Copyright (c) 1995 Microsoft Corporation
> > > Module Name:
> > > I82930.c
> > > Abstract:
> > > USB device driver for Intel 82930 USB test board
> > > Environment:
> > > kernel mode only
> > >
> > > So if you have access to or can get the MS DDK then I think it has all

> you
> > > need.
> > > Our setup was pretty much done for us, but you need to compile this

> driver
> > > with a unique filename and maybe your USB ID (not sure about this) and

> > then
> > > you setup a .inf file that says your device uses this driver file.
> > > (executable renamed to SneakersUSB.SYS or such)
> > >
> > > "your device" is the name that should show up even without a driver

when
> > you
> > > plug it into a Windows box. I assume the USB core has some default.

> (.inf
> > > file basically maps this name to which driver to load. May be able to

> use
> > > someone elses driver by creating a .inf for all I know)
> > >
> > > Surprised they gave away the core, but not the driver they tested it

> with.
> > >
> > > Good Luck!
> > > Ken
> > >
> > >
> > >
> > >
> > > "SneakerNet" <[email protected]> wrote in message
> > > news:[email protected]
> > > > Hello again Paul ;o)
> > > >
> > > > LOL, tell you what, I already cracked it. I found that document

> sometime
> > > > back now *grins*.
> > > > And I also cracked that the CLKDLL is just a pll *grins again* and

> thus
> > I
> > > > had posted another msg (which you have already replied before) but

> once
> > > > again I beat you to it. I cracked it before you replied ;o).
> > > >
> > > > Anyway thanks for taking time in explaning the Xilinx components.
> > > > Regarding the free USB Cores from Altera website.
> > > > Service I would give umm 10% *no offence*. I had to log into that

page
> > and
> > > > request the core nearly 10 times before someone contacted me from

> > Altera.
> > > > Then after 2-3 days they told me that USB 2.0 core is not functional

> so
> > i
> > > > asked for usb 1.1 core. Then they asked me hundreds of questions of
> > > why/what
> > > > for/how long etc etc. When I finally got it, it was only licenced

for
> a
> > > > month (which passes by just like that as I'm working on this USB

> project
> > > > part time.
> > > > Anyway I found a site that had the full VHDL USB core free of cost
> > > (without
> > > > any need for any hardware). I'm stuck at the windows driver now.

Rest
> is
> > > all
> > > > ready to go..
> > > >
> > > > Any help on how to install a generic usb driver?
> > > >
> > > > Thanks for your response Paul.
> > > > Bye
> > > >
> > > > "Paul Leventis" <[email protected]> wrote in message
> > > > news:[email protected] able.rogers.com...
> > > > > Hi SneakerNet,
> > > > >
> > > > > I just noticed we have VERY handy application note for you --

AN307
> > > > > (available on www.altera.com) describes how to migrate from a

Xilinx
> > > > design
> > > > > to an Altera design. There is a section dedicated to DLL to PLL
> > > > conversion
> > > > > that should be able to help you out. Below is my attempt at

> > explaining
> > > > > things before I found this app note.
> > > > >
> > > > > In Altera's FPGAs, we've got PLLs, which provide a superset of the
> > > CLKDLL
> > > > > function you're trying to use. You'd want to setup your PLL to

use
> > > CLKIN
> > > > as
> > > > > its input inclk0, hook up the C0 port to GCLK signal and C1 port

to
> > CLK
> > > > > signal, don't apply any phase shift, and use the C0 port to

> compensate
> > > the
> > > > > PLL output. Connect RST to the areset port, and LOCKED to the

> locked
> > > > port.
> > > > > You'll want to setup your C1 port to have a 2x frequency

multiplier
> on
> > > it.
> > > > > The Lock and Reset signals have some sort of equivalent that I

can't
> > > > recall.
> > > > > You can do this all through the allpll megafunction.
> > > > >
> > > > > The BUFGs are not necessary in Altera parts. In Xilinx parts,

these
> > > > buffers
> > > > > are needed to explicitly indicate that you want a signal to be

> driven
> > > onto
> > > > > the global clock network. Quartus allows you to make "global"
> > > assignments
> > > > > to nets, but it automatically promotes anything it finds that

looks
> > like
> > > a
> > > > > clock net, as well as high-fanout or asynchronous signals if there

> are
> > > > > enough global clocks available. The PLL output nets will be
> > > automatically
> > > > > promoted to global clock nets for you, and the PLL input will be
> > > assigned
> > > > to
> > > > > the associated input clock pin.
> > > > >
> > > > > Also, I should point out that there are four USB cores listed on

our
> > > > > Intellectual Property page (www.altera.com) under Interfaces &
> > > Peripherals
> > > > > under USB. All are available for free trial under our OpenCore
> > > evaluation
> > > > > program.
> > > > >
> > > > > Regards,
> > > > >
> > > > > Paul Leventis
> > > > > Altera Corp.
> > > > >
> > > > >
> > > > > "SneakerNet" <[email protected]> wrote in message
> > > > > news:[email protected]
> > > > > > Hi Antti
> > > > > > Thanks for the response.
> > > > > > haha. I don't expect anyone to do work for me, othwersie I won't

> > learn
> > > > > > anything, but I wouldn't mind some guidance along the way from

you
> > > > guys..
> > > > > > Anyway I need to ask 2 questions regarding your reply.
> > > > > > 1. When you say USB11T11A, do you mean the Philips tranceiver
> > > > PDIUSBP11A?
> > > > > If
> > > > > > no then I'm sorry but i'm not able to find anything on

USB11T11A.
> > Have
> > > I
> > > > > > gone blind?
> > > > > > 2. Regarding the usb (japanese design), I have ended up towards

a
> > > brick
> > > > > > wall. What I mean to say is, I have been looking at the design

for
> > > > couple
> > > > > of
> > > > > > hours and there are 4 components that I'm not sure what they do.

> The
> > > > main
> > > > > > problem is that the code was written for a Xilinx component and
> > > because
> > > > > I'm
> > > > > > using Altera component, I'm do not have the librabires that

these
> > > > > component
> > > > > > are using.
> > > > > > Firstly the library defined is (which is for Xilinx only (pls

> > correct
> > > me
> > > > > if
> > > > > > i'm wrong))
> > > > > > library unisim;
> > > > > > use unisim.vcomponents.all;
> > > > > >
> > > > > > and the 4 components that are using this library are
> > > > > > u_DLL : CLKDLL
> > > > > > port map ( CLKIN => CLKINM,
> > > > > > CLKFB => GCLK,
> > > > > > RST => RST,
> > > > > > CLK0 => GCLKM,
> > > > > > CLK2X => CLKM,
> > > > > > LOCKED => LOCK
> > > > > > );
> > > > > >
> > > > > > u_GCLK : BUFG
> > > > > > port map ( I => GCLKM,
> > > > > > O => GCLK
> > > > > > );
> > > > > >
> > > > > > u_CLK : BUFG
> > > > > > port map ( I => CLKM,
> > > > > > O => CLK
> > > > > > );
> > > > > >
> > > > > > u_CLKIN : IBUFG
> > > > > > port map ( I => CLKIN,
> > > > > > O => CLKINM
> > > > > > );
> > > > > >
> > > > > > If you can explain me how I can replace these components for

> Altera
> > > > > design,
> > > > > > I will have a step to progress. If I can get past this point,

then
> I
> > > > have
> > > > > > something to try on the chip and play around. My problem is that

> > right
> > > > now
> > > > > I
> > > > > > can't go past compiling as Quartus doesn't recognize these

> > components
> > > > (or
> > > > > > the library). Pls Advice
> > > > > >
> > > > > > Thanks again
> > > > > >
> > > > > > Regards
> > > > > >
> > > > > >
> > > > > > "Antti Lukats" <[email protected]> wrote in message
> > > > > > news:[email protected] om...
> > > > > > > "SneakerNet" <[email protected]> wrote in message

> > news:<p43cb.157047
> > > > > > > > Has anyone successfully implemented USB 2.0 or USB 1.1

> protocol
> > in
> > > > > > > [deleted]
> > > > > > >
> > > > > > > USB11T11A FS/LS USB tranceiver
> > > > > > >
> > > > > > > usb_phy (opencores) UTMI interface that connects to USB11T11A
> > > > > > >
> > > > > > > usb1.1 (opencores) connects to usb_phy (opencores) connects to
> > > > > > > USB11T1A it is not HID but it will enumerate in hardware iw

the
> > USB
> > > > > > > host will 'see' it, but ther is no host software provide
> > > > > > >
> > > > > > > usb (japanase desing) full HID USB core includes USB11T1A

model)
> > can
> > > > > > > directly be connected to usb D+ D- pins! (no tranceiver chip),

> > there
> > > > > > > is some VB test program to talk to the core (as it is HID
> > > peripheral)
> > > > > > >
> > > > > > > antti
> > > > > > > PS I am afraid you have todo some homework cant do it for

you
> > > > > >
> > > > > >
> > > > >
> > > > >
> > > >
> > > >
> > >
> > >

> >
> >

>
>



Reply With Quote
  #17 (permalink)  
Old 10-01-2003, 02:38 AM
Kenneth Land
Guest
 
Posts: n/a
Default Re: USB 1.1/2.0 Implementation

Hey,

Sorry, my cheapy supernews account doesn't support attachments or .jpgs.
(text only)

The Jongo stuff sounds cool if it would work. I'm not going to be able to
rebuild our driver for awhile. I'll have to find the machine at work that
has the DDK installed. (My machine doesn't)

Interestingly our vendor/device id's don't exist in the driver source, only
the driver name.

Is Jongo free? Sounds interesting. I was wondering why there isn't a
generice bulk interface driver in Windows that you could use to talk to any
USB device. I'm wondering if its not possible. If our vendor/device id's
are only in our .inf file then that would mean anyone could map their device
to use an existing driver just by editting the .inf file.

As you may guess, I wasn't the guy who originally built our sample Netchip
driver many years ago. (I was the guy who got the registered ID's in the
first place) I know it was easy and it works great. I'll update you if I
make any more progress.

Ken


"SneakerNet" <[email protected]> wrote in message
news:[email protected]
> Hi Ken
> Ok when i plug in the cable, windows reports a usb device is found, but
> because win doesn' know what it is, it fails. I have attached a screenshot
> (Sample.jpg, sorry about the attachment but I don't have web space to

upload
> on a site).
>
> Now someone also mentioned to use Jongo WinDriver which I'm trying to use
> it.
> Firstly have u used this program your self. If you haven't used it then
> reject the next line.
> Secondly, this program allows you to generate a custom inf file (with
> product and vendor id), which I do but when it comes to installing the new
> custom driver, win2k doesn't like it and instead uses the
> c:\winnt\inf\usb.inf file. This sucks.
>
>
> Do you know what 'multi-interface device' means?
> Cheers Ken
> Regards
>
> "Kenneth Land" <[email protected]> wrote in message
> news:[email protected]
> >
> > So, when you plugin your device, does Windows say New Device Found,

etc.?
> > Giving you a chance to install a driver? If so, does it tell you the

name
> > of the device?
> >
> > I"ve never built our driver, but I'll give it the ol' 15 minute try.
> >
> > Ken
> >
> > "SneakerNet" <[email protected]> wrote in message
> > news:[email protected]news.xtra.co.nz...
> > > Hi Ken
> > >
> > > Thanks for the important tip. I'll give that a shot. (so there is no

way
> u
> > > can send me driver? all i need is a driver with vendor id = 0c91 and

> > product
> > > id = 2001).
> > > Anyway like u mentioned, very big pity that the guys didn't include

> > drivers
> > > and they gave their whole vhdl code free. Pity!
> > >
> > > Hope god has mercy on my soul while i'm doing usb driver.. LOL
> > > Thanks Ken
> > > Kind Regards
> > >
> > >
> > >
> > > "Ken Land" <[email protected]> wrote in message
> > > news:[email protected]
> > > > Hey Sneaker,
> > > >
> > > > I can't give you the code to our host side driver (I don't own it)

but
> I
> > > can
> > > > tell you its a slight modification to a sample driver in the

MicroSoft
> > > > Device Driver Kit.
> > > >
> > > > From the original header. (So you could search)
> > > >
> > > > Copyright (c) 1995 Microsoft Corporation
> > > > Module Name:
> > > > I82930.c
> > > > Abstract:
> > > > USB device driver for Intel 82930 USB test board
> > > > Environment:
> > > > kernel mode only
> > > >
> > > > So if you have access to or can get the MS DDK then I think it has

all
> > you
> > > > need.
> > > > Our setup was pretty much done for us, but you need to compile this

> > driver
> > > > with a unique filename and maybe your USB ID (not sure about this)

and
> > > then
> > > > you setup a .inf file that says your device uses this driver file.
> > > > (executable renamed to SneakersUSB.SYS or such)
> > > >
> > > > "your device" is the name that should show up even without a driver

> when
> > > you
> > > > plug it into a Windows box. I assume the USB core has some default.

> > (.inf
> > > > file basically maps this name to which driver to load. May be able

to
> > use
> > > > someone elses driver by creating a .inf for all I know)
> > > >
> > > > Surprised they gave away the core, but not the driver they tested it

> > with.
> > > >
> > > > Good Luck!
> > > > Ken
> > > >
> > > >
> > > >
> > > >
> > > > "SneakerNet" <[email protected]> wrote in message
> > > > news:[email protected]
> > > > > Hello again Paul ;o)
> > > > >
> > > > > LOL, tell you what, I already cracked it. I found that document

> > sometime
> > > > > back now *grins*.
> > > > > And I also cracked that the CLKDLL is just a pll *grins again* and

> > thus
> > > I
> > > > > had posted another msg (which you have already replied before) but

> > once
> > > > > again I beat you to it. I cracked it before you replied ;o).
> > > > >
> > > > > Anyway thanks for taking time in explaning the Xilinx components.
> > > > > Regarding the free USB Cores from Altera website.
> > > > > Service I would give umm 10% *no offence*. I had to log into that

> page
> > > and
> > > > > request the core nearly 10 times before someone contacted me from
> > > Altera.
> > > > > Then after 2-3 days they told me that USB 2.0 core is not

functional
> > so
> > > i
> > > > > asked for usb 1.1 core. Then they asked me hundreds of questions

of
> > > > why/what
> > > > > for/how long etc etc. When I finally got it, it was only licenced

> for
> > a
> > > > > month (which passes by just like that as I'm working on this USB

> > project
> > > > > part time.
> > > > > Anyway I found a site that had the full VHDL USB core free of cost
> > > > (without
> > > > > any need for any hardware). I'm stuck at the windows driver now.

> Rest
> > is
> > > > all
> > > > > ready to go..
> > > > >
> > > > > Any help on how to install a generic usb driver?
> > > > >
> > > > > Thanks for your response Paul.
> > > > > Bye
> > > > >
> > > > > "Paul Leventis" <[email protected]> wrote in message
> > > > >

news:[email protected] able.rogers.com...
> > > > > > Hi SneakerNet,
> > > > > >
> > > > > > I just noticed we have VERY handy application note for you --

> AN307
> > > > > > (available on www.altera.com) describes how to migrate from a

> Xilinx
> > > > > design
> > > > > > to an Altera design. There is a section dedicated to DLL to PLL
> > > > > conversion
> > > > > > that should be able to help you out. Below is my attempt at
> > > explaining
> > > > > > things before I found this app note.
> > > > > >
> > > > > > In Altera's FPGAs, we've got PLLs, which provide a superset of

the
> > > > CLKDLL
> > > > > > function you're trying to use. You'd want to setup your PLL to

> use
> > > > CLKIN
> > > > > as
> > > > > > its input inclk0, hook up the C0 port to GCLK signal and C1 port

> to
> > > CLK
> > > > > > signal, don't apply any phase shift, and use the C0 port to

> > compensate
> > > > the
> > > > > > PLL output. Connect RST to the areset port, and LOCKED to the

> > locked
> > > > > port.
> > > > > > You'll want to setup your C1 port to have a 2x frequency

> multiplier
> > on
> > > > it.
> > > > > > The Lock and Reset signals have some sort of equivalent that I

> can't
> > > > > recall.
> > > > > > You can do this all through the allpll megafunction.
> > > > > >
> > > > > > The BUFGs are not necessary in Altera parts. In Xilinx parts,

> these
> > > > > buffers
> > > > > > are needed to explicitly indicate that you want a signal to be

> > driven
> > > > onto
> > > > > > the global clock network. Quartus allows you to make "global"
> > > > assignments
> > > > > > to nets, but it automatically promotes anything it finds that

> looks
> > > like
> > > > a
> > > > > > clock net, as well as high-fanout or asynchronous signals if

there
> > are
> > > > > > enough global clocks available. The PLL output nets will be
> > > > automatically
> > > > > > promoted to global clock nets for you, and the PLL input will be
> > > > assigned
> > > > > to
> > > > > > the associated input clock pin.
> > > > > >
> > > > > > Also, I should point out that there are four USB cores listed on

> our
> > > > > > Intellectual Property page (www.altera.com) under Interfaces &
> > > > Peripherals
> > > > > > under USB. All are available for free trial under our OpenCore
> > > > evaluation
> > > > > > program.
> > > > > >
> > > > > > Regards,
> > > > > >
> > > > > > Paul Leventis
> > > > > > Altera Corp.
> > > > > >
> > > > > >
> > > > > > "SneakerNet" <[email protected]> wrote in message
> > > > > > news:[email protected]
> > > > > > > Hi Antti
> > > > > > > Thanks for the response.
> > > > > > > haha. I don't expect anyone to do work for me, othwersie I

won't
> > > learn
> > > > > > > anything, but I wouldn't mind some guidance along the way from

> you
> > > > > guys..
> > > > > > > Anyway I need to ask 2 questions regarding your reply.
> > > > > > > 1. When you say USB11T11A, do you mean the Philips tranceiver
> > > > > PDIUSBP11A?
> > > > > > If
> > > > > > > no then I'm sorry but i'm not able to find anything on

> USB11T11A.
> > > Have
> > > > I
> > > > > > > gone blind?
> > > > > > > 2. Regarding the usb (japanese design), I have ended up

towards
> a
> > > > brick
> > > > > > > wall. What I mean to say is, I have been looking at the design

> for
> > > > > couple
> > > > > > of
> > > > > > > hours and there are 4 components that I'm not sure what they

do.
> > The
> > > > > main
> > > > > > > problem is that the code was written for a Xilinx component

and
> > > > because
> > > > > > I'm
> > > > > > > using Altera component, I'm do not have the librabires that

> these
> > > > > > component
> > > > > > > are using.
> > > > > > > Firstly the library defined is (which is for Xilinx only (pls
> > > correct
> > > > me
> > > > > > if
> > > > > > > i'm wrong))
> > > > > > > library unisim;
> > > > > > > use unisim.vcomponents.all;
> > > > > > >
> > > > > > > and the 4 components that are using this library are
> > > > > > > u_DLL : CLKDLL
> > > > > > > port map ( CLKIN => CLKINM,
> > > > > > > CLKFB => GCLK,
> > > > > > > RST => RST,
> > > > > > > CLK0 => GCLKM,
> > > > > > > CLK2X => CLKM,
> > > > > > > LOCKED => LOCK
> > > > > > > );
> > > > > > >
> > > > > > > u_GCLK : BUFG
> > > > > > > port map ( I => GCLKM,
> > > > > > > O => GCLK
> > > > > > > );
> > > > > > >
> > > > > > > u_CLK : BUFG
> > > > > > > port map ( I => CLKM,
> > > > > > > O => CLK
> > > > > > > );
> > > > > > >
> > > > > > > u_CLKIN : IBUFG
> > > > > > > port map ( I => CLKIN,
> > > > > > > O => CLKINM
> > > > > > > );
> > > > > > >
> > > > > > > If you can explain me how I can replace these components for

> > Altera
> > > > > > design,
> > > > > > > I will have a step to progress. If I can get past this point,

> then
> > I
> > > > > have
> > > > > > > something to try on the chip and play around. My problem is

that
> > > right
> > > > > now
> > > > > > I
> > > > > > > can't go past compiling as Quartus doesn't recognize these
> > > components
> > > > > (or
> > > > > > > the library). Pls Advice
> > > > > > >
> > > > > > > Thanks again
> > > > > > >
> > > > > > > Regards
> > > > > > >
> > > > > > >
> > > > > > > "Antti Lukats" <[email protected]> wrote in message
> > > > > > > news:[email protected] om...
> > > > > > > > "SneakerNet" <[email protected]> wrote in message
> > > news:<p43cb.157047
> > > > > > > > > Has anyone successfully implemented USB 2.0 or USB 1.1

> > protocol
> > > in
> > > > > > > > [deleted]
> > > > > > > >
> > > > > > > > USB11T11A FS/LS USB tranceiver
> > > > > > > >
> > > > > > > > usb_phy (opencores) UTMI interface that connects to

USB11T11A
> > > > > > > >
> > > > > > > > usb1.1 (opencores) connects to usb_phy (opencores) connects

to
> > > > > > > > USB11T1A it is not HID but it will enumerate in hardware iw

> the
> > > USB
> > > > > > > > host will 'see' it, but ther is no host software provide
> > > > > > > >
> > > > > > > > usb (japanase desing) full HID USB core includes USB11T1A

> model)
> > > can
> > > > > > > > directly be connected to usb D+ D- pins! (no tranceiver

chip),
> > > there
> > > > > > > > is some VB test program to talk to the core (as it is HID
> > > > peripheral)
> > > > > > > >
> > > > > > > > antti
> > > > > > > > PS I am afraid you have todo some homework cant do it for

> you
> > > > > > >
> > > > > > >
> > > > > >
> > > > > >
> > > > >
> > > > >
> > > >
> > > >
> > >
> > >

> >
> >

>
>



Reply With Quote
  #18 (permalink)  
Old 10-01-2003, 03:23 AM
SneakerNet
Guest
 
Posts: n/a
Default Re: USB 1.1/2.0 Implementation

Hi Ken
The Jongo windriver is free for 30 days, but a quick hunt on
www.astalavista.box.sk found the never ending patch.
I can send you the program + patch if u'r interested. Let me Know..

The program does sound very cool, excpect I can't get it to work *sniff*.
You are right about the ID's. I suspect the .sys and .dll files prob have
the ID's as well in it.
Then again I'm no guru at windows driver.. aaargghh .. why does this have to
be so unfriendly..
any more help pls pls drop in a line

Regards

"Kenneth Land" <[email protected]> wrote in message
news:[email protected]s.com...
> Hey,
>
> Sorry, my cheapy supernews account doesn't support attachments or .jpgs.
> (text only)
>
> The Jongo stuff sounds cool if it would work. I'm not going to be able to
> rebuild our driver for awhile. I'll have to find the machine at work that
> has the DDK installed. (My machine doesn't)
>
> Interestingly our vendor/device id's don't exist in the driver source,

only
> the driver name.
>
> Is Jongo free? Sounds interesting. I was wondering why there isn't a
> generice bulk interface driver in Windows that you could use to talk to

any
> USB device. I'm wondering if its not possible. If our vendor/device id's
> are only in our .inf file then that would mean anyone could map their

device
> to use an existing driver just by editting the .inf file.
>
> As you may guess, I wasn't the guy who originally built our sample Netchip
> driver many years ago. (I was the guy who got the registered ID's in the
> first place) I know it was easy and it works great. I'll update you if I
> make any more progress.
>
> Ken
>
>
> "SneakerNet" <[email protected]> wrote in message
> news:[email protected]
> > Hi Ken
> > Ok when i plug in the cable, windows reports a usb device is found, but
> > because win doesn' know what it is, it fails. I have attached a

screenshot
> > (Sample.jpg, sorry about the attachment but I don't have web space to

> upload
> > on a site).
> >
> > Now someone also mentioned to use Jongo WinDriver which I'm trying to

use
> > it.
> > Firstly have u used this program your self. If you haven't used it then
> > reject the next line.
> > Secondly, this program allows you to generate a custom inf file (with
> > product and vendor id), which I do but when it comes to installing the

new
> > custom driver, win2k doesn't like it and instead uses the
> > c:\winnt\inf\usb.inf file. This sucks.
> >
> >
> > Do you know what 'multi-interface device' means?
> > Cheers Ken
> > Regards
> >
> > "Kenneth Land" <[email protected]> wrote in message
> > news:[email protected]
> > >
> > > So, when you plugin your device, does Windows say New Device Found,

> etc.?
> > > Giving you a chance to install a driver? If so, does it tell you the

> name
> > > of the device?
> > >
> > > I"ve never built our driver, but I'll give it the ol' 15 minute try.
> > >
> > > Ken
> > >
> > > "SneakerNet" <[email protected]> wrote in message
> > > news:[email protected]
> > > > Hi Ken
> > > >
> > > > Thanks for the important tip. I'll give that a shot. (so there is no

> way
> > u
> > > > can send me driver? all i need is a driver with vendor id = 0c91 and
> > > product
> > > > id = 2001).
> > > > Anyway like u mentioned, very big pity that the guys didn't include
> > > drivers
> > > > and they gave their whole vhdl code free. Pity!
> > > >
> > > > Hope god has mercy on my soul while i'm doing usb driver.. LOL
> > > > Thanks Ken
> > > > Kind Regards
> > > >
> > > >
> > > >
> > > > "Ken Land" <[email protected]> wrote in message
> > > > news:[email protected]
> > > > > Hey Sneaker,
> > > > >
> > > > > I can't give you the code to our host side driver (I don't own it)

> but
> > I
> > > > can
> > > > > tell you its a slight modification to a sample driver in the

> MicroSoft
> > > > > Device Driver Kit.
> > > > >
> > > > > From the original header. (So you could search)
> > > > >
> > > > > Copyright (c) 1995 Microsoft Corporation
> > > > > Module Name:
> > > > > I82930.c
> > > > > Abstract:
> > > > > USB device driver for Intel 82930 USB test board
> > > > > Environment:
> > > > > kernel mode only
> > > > >
> > > > > So if you have access to or can get the MS DDK then I think it has

> all
> > > you
> > > > > need.
> > > > > Our setup was pretty much done for us, but you need to compile

this
> > > driver
> > > > > with a unique filename and maybe your USB ID (not sure about this)

> and
> > > > then
> > > > > you setup a .inf file that says your device uses this driver file.
> > > > > (executable renamed to SneakersUSB.SYS or such)
> > > > >
> > > > > "your device" is the name that should show up even without a

driver
> > when
> > > > you
> > > > > plug it into a Windows box. I assume the USB core has some

default.
> > > (.inf
> > > > > file basically maps this name to which driver to load. May be

able
> to
> > > use
> > > > > someone elses driver by creating a .inf for all I know)
> > > > >
> > > > > Surprised they gave away the core, but not the driver they tested

it
> > > with.
> > > > >
> > > > > Good Luck!
> > > > > Ken
> > > > >
> > > > >
> > > > >
> > > > >
> > > > > "SneakerNet" <[email protected]> wrote in message
> > > > > news:[email protected]
> > > > > > Hello again Paul ;o)
> > > > > >
> > > > > > LOL, tell you what, I already cracked it. I found that document
> > > sometime
> > > > > > back now *grins*.
> > > > > > And I also cracked that the CLKDLL is just a pll *grins again*

and
> > > thus
> > > > I
> > > > > > had posted another msg (which you have already replied before)

but
> > > once
> > > > > > again I beat you to it. I cracked it before you replied ;o).
> > > > > >
> > > > > > Anyway thanks for taking time in explaning the Xilinx

components.
> > > > > > Regarding the free USB Cores from Altera website.
> > > > > > Service I would give umm 10% *no offence*. I had to log into

that
> > page
> > > > and
> > > > > > request the core nearly 10 times before someone contacted me

from
> > > > Altera.
> > > > > > Then after 2-3 days they told me that USB 2.0 core is not

> functional
> > > so
> > > > i
> > > > > > asked for usb 1.1 core. Then they asked me hundreds of questions

> of
> > > > > why/what
> > > > > > for/how long etc etc. When I finally got it, it was only

licenced
> > for
> > > a
> > > > > > month (which passes by just like that as I'm working on this USB
> > > project
> > > > > > part time.
> > > > > > Anyway I found a site that had the full VHDL USB core free of

cost
> > > > > (without
> > > > > > any need for any hardware). I'm stuck at the windows driver now.

> > Rest
> > > is
> > > > > all
> > > > > > ready to go..
> > > > > >
> > > > > > Any help on how to install a generic usb driver?
> > > > > >
> > > > > > Thanks for your response Paul.
> > > > > > Bye
> > > > > >
> > > > > > "Paul Leventis" <[email protected]> wrote in message
> > > > > >

> news:[email protected] able.rogers.com...
> > > > > > > Hi SneakerNet,
> > > > > > >
> > > > > > > I just noticed we have VERY handy application note for you --

> > AN307
> > > > > > > (available on www.altera.com) describes how to migrate from a

> > Xilinx
> > > > > > design
> > > > > > > to an Altera design. There is a section dedicated to DLL to

PLL
> > > > > > conversion
> > > > > > > that should be able to help you out. Below is my attempt at
> > > > explaining
> > > > > > > things before I found this app note.
> > > > > > >
> > > > > > > In Altera's FPGAs, we've got PLLs, which provide a superset of

> the
> > > > > CLKDLL
> > > > > > > function you're trying to use. You'd want to setup your PLL

to
> > use
> > > > > CLKIN
> > > > > > as
> > > > > > > its input inclk0, hook up the C0 port to GCLK signal and C1

port
> > to
> > > > CLK
> > > > > > > signal, don't apply any phase shift, and use the C0 port to
> > > compensate
> > > > > the
> > > > > > > PLL output. Connect RST to the areset port, and LOCKED to the
> > > locked
> > > > > > port.
> > > > > > > You'll want to setup your C1 port to have a 2x frequency

> > multiplier
> > > on
> > > > > it.
> > > > > > > The Lock and Reset signals have some sort of equivalent that I

> > can't
> > > > > > recall.
> > > > > > > You can do this all through the allpll megafunction.
> > > > > > >
> > > > > > > The BUFGs are not necessary in Altera parts. In Xilinx parts,

> > these
> > > > > > buffers
> > > > > > > are needed to explicitly indicate that you want a signal to be
> > > driven
> > > > > onto
> > > > > > > the global clock network. Quartus allows you to make "global"
> > > > > assignments
> > > > > > > to nets, but it automatically promotes anything it finds that

> > looks
> > > > like
> > > > > a
> > > > > > > clock net, as well as high-fanout or asynchronous signals if

> there
> > > are
> > > > > > > enough global clocks available. The PLL output nets will be
> > > > > automatically
> > > > > > > promoted to global clock nets for you, and the PLL input will

be
> > > > > assigned
> > > > > > to
> > > > > > > the associated input clock pin.
> > > > > > >
> > > > > > > Also, I should point out that there are four USB cores listed

on
> > our
> > > > > > > Intellectual Property page (www.altera.com) under Interfaces &
> > > > > Peripherals
> > > > > > > under USB. All are available for free trial under our

OpenCore
> > > > > evaluation
> > > > > > > program.
> > > > > > >
> > > > > > > Regards,
> > > > > > >
> > > > > > > Paul Leventis
> > > > > > > Altera Corp.
> > > > > > >
> > > > > > >
> > > > > > > "SneakerNet" <[email protected]> wrote in message
> > > > > > > news:[email protected]
> > > > > > > > Hi Antti
> > > > > > > > Thanks for the response.
> > > > > > > > haha. I don't expect anyone to do work for me, othwersie I

> won't
> > > > learn
> > > > > > > > anything, but I wouldn't mind some guidance along the way

from
> > you
> > > > > > guys..
> > > > > > > > Anyway I need to ask 2 questions regarding your reply.
> > > > > > > > 1. When you say USB11T11A, do you mean the Philips

tranceiver
> > > > > > PDIUSBP11A?
> > > > > > > If
> > > > > > > > no then I'm sorry but i'm not able to find anything on

> > USB11T11A.
> > > > Have
> > > > > I
> > > > > > > > gone blind?
> > > > > > > > 2. Regarding the usb (japanese design), I have ended up

> towards
> > a
> > > > > brick
> > > > > > > > wall. What I mean to say is, I have been looking at the

design
> > for
> > > > > > couple
> > > > > > > of
> > > > > > > > hours and there are 4 components that I'm not sure what they

> do.
> > > The
> > > > > > main
> > > > > > > > problem is that the code was written for a Xilinx component

> and
> > > > > because
> > > > > > > I'm
> > > > > > > > using Altera component, I'm do not have the librabires that

> > these
> > > > > > > component
> > > > > > > > are using.
> > > > > > > > Firstly the library defined is (which is for Xilinx only

(pls
> > > > correct
> > > > > me
> > > > > > > if
> > > > > > > > i'm wrong))
> > > > > > > > library unisim;
> > > > > > > > use unisim.vcomponents.all;
> > > > > > > >
> > > > > > > > and the 4 components that are using this library are
> > > > > > > > u_DLL : CLKDLL
> > > > > > > > port map ( CLKIN => CLKINM,
> > > > > > > > CLKFB => GCLK,
> > > > > > > > RST => RST,
> > > > > > > > CLK0 => GCLKM,
> > > > > > > > CLK2X => CLKM,
> > > > > > > > LOCKED => LOCK
> > > > > > > > );
> > > > > > > >
> > > > > > > > u_GCLK : BUFG
> > > > > > > > port map ( I => GCLKM,
> > > > > > > > O => GCLK
> > > > > > > > );
> > > > > > > >
> > > > > > > > u_CLK : BUFG
> > > > > > > > port map ( I => CLKM,
> > > > > > > > O => CLK
> > > > > > > > );
> > > > > > > >
> > > > > > > > u_CLKIN : IBUFG
> > > > > > > > port map ( I => CLKIN,
> > > > > > > > O => CLKINM
> > > > > > > > );
> > > > > > > >
> > > > > > > > If you can explain me how I can replace these components for
> > > Altera
> > > > > > > design,
> > > > > > > > I will have a step to progress. If I can get past this

point,
> > then
> > > I
> > > > > > have
> > > > > > > > something to try on the chip and play around. My problem is

> that
> > > > right
> > > > > > now
> > > > > > > I
> > > > > > > > can't go past compiling as Quartus doesn't recognize these
> > > > components
> > > > > > (or
> > > > > > > > the library). Pls Advice
> > > > > > > >
> > > > > > > > Thanks again
> > > > > > > >
> > > > > > > > Regards
> > > > > > > >
> > > > > > > >
> > > > > > > > "Antti Lukats" <[email protected]> wrote in message
> > > > > > > > news:[email protected] om...
> > > > > > > > > "SneakerNet" <[email protected]> wrote in message
> > > > news:<p43cb.157047
> > > > > > > > > > Has anyone successfully implemented USB 2.0 or USB 1.1
> > > protocol
> > > > in
> > > > > > > > > [deleted]
> > > > > > > > >
> > > > > > > > > USB11T11A FS/LS USB tranceiver
> > > > > > > > >
> > > > > > > > > usb_phy (opencores) UTMI interface that connects to

> USB11T11A
> > > > > > > > >
> > > > > > > > > usb1.1 (opencores) connects to usb_phy (opencores)

connects
> to
> > > > > > > > > USB11T1A it is not HID but it will enumerate in hardware

iw
> > the
> > > > USB
> > > > > > > > > host will 'see' it, but ther is no host software provide
> > > > > > > > >
> > > > > > > > > usb (japanase desing) full HID USB core includes USB11T1A

> > model)
> > > > can
> > > > > > > > > directly be connected to usb D+ D- pins! (no tranceiver

> chip),
> > > > there
> > > > > > > > > is some VB test program to talk to the core (as it is HID
> > > > > peripheral)
> > > > > > > > >
> > > > > > > > > antti
> > > > > > > > > PS I am afraid you have todo some homework cant do it

for
> > you
> > > > > > > >
> > > > > > > >
> > > > > > >
> > > > > > >
> > > > > >
> > > > > >
> > > > >
> > > > >
> > > >
> > > >
> > >
> > >

> >
> >

>
>



Reply With Quote
  #19 (permalink)  
Old 10-01-2003, 05:21 AM
Joe Chisolm
Guest
 
Posts: n/a
Default Re: USB 1.1/2.0 Implementation

SneakerNet wrote:

> Hi Ken
>
> Thanks for the important tip. I'll give that a shot. (so there is no way u
> can send me driver? all i need is a driver with vendor id = 0c91 and
> product id = 2001).
> Anyway like u mentioned, very big pity that the guys didn't include
> drivers and they gave their whole vhdl code free. Pity!
>
> Hope god has mercy on my soul while i'm doing usb driver.. LOL
> Thanks Ken
> Kind Regards

[snip]

You might look for a book by the title (I think) "UBS made easy" or
something like that. My copy must be packed away. It had a lot of
info on Windows drivers and included several VB examples on the CD.
If I can find the book I'll post the ISBN but I remember I got it
from Amazon.

--
Joe Chisolm - Arizona

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