FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > FPGA

FPGA comp.arch.fpga newsgroup (usenet)

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 01-13-2004, 10:07 AM
guille
Guest
 
Posts: n/a
Default 'universal delay' term in Xilinx parts

Hi all,

Sorry if this question is a bit too Xilinx-specific

In the Xilinx datasheets there is a term, called the "universal
delay" (tUDA) for which I cannot find a description anywhere.

The problem with this one is that in the timing model there are
two paths that go from the 'combinatorial logic' block to the
output buffer, one directly and one traversing the tUDA block,
but it doesn't seem to be documented which path is used in each
particular case.

When I look at the timing report produced by the ISE tools, I see
that this factor has been added in the calculation of certain
pad to pad propagation delays, but not for all of them. I cannot
find a pattern on when is this tUDA factor added.

Does someone know what is this tUDA thing and when is it used?

Thanks,
Guillermo Rodriguez
Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
Re: 5 volt tolerant Xilinx parts Neeraj Varma FPGA 3 08-30-2003 03:13 PM
Xilinx ISE drops support for more parts lecroy FPGA 30 07-09-2003 04:57 PM


All times are GMT +1. The time now is 01:35 AM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2021, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved