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Old 01-13-2004, 10:07 AM
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Default 'universal delay' term in Xilinx parts

Hi all,

Sorry if this question is a bit too Xilinx-specific

In the Xilinx datasheets there is a term, called the "universal
delay" (tUDA) for which I cannot find a description anywhere.

The problem with this one is that in the timing model there are
two paths that go from the 'combinatorial logic' block to the
output buffer, one directly and one traversing the tUDA block,
but it doesn't seem to be documented which path is used in each
particular case.

When I look at the timing report produced by the ISE tools, I see
that this factor has been added in the calculation of certain
pad to pad propagation delays, but not for all of them. I cannot
find a pattern on when is this tUDA factor added.

Does someone know what is this tUDA thing and when is it used?

Guillermo Rodriguez
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