FPGA Central

I know have a working IDE interface utilizing the PIO transfer mode.
I'm only concerned with writing data so it is only using the 30h write
sectors command and it is working well with an old 4gb drive I have.

I've been trying to write some VHDL code for the dma start, sustain,
and end sequences but its really not going smoothly. I have multiple
programs writen in vhdl and then I create symbols for them and wire
them together in a schematic. Problem is I can't get anything to
simulate now at all no matter what I do

I'm kind of a newbie to vhdl, as I'm only a student and only started
with this stuff a few months ago but is their a better way to connect
these programs together than the schematic that will simulate or is it
not simulating likly because the code is written badly?

I know its not much to go on but any help would be apperciated

Keith Wakeham

[email protected] wrote:

> Problem is I can't get anything to
> simulate now at all no matter what I do

I'm not really sure what you mean by "won't simulate"?

> I'm kind of a newbie to vhdl, as I'm only a student and only started
> with this stuff a few months ago but is their a better way to connect
> these programs together than the schematic that will simulate or is
> it not simulating likly because the code is written badly?

There's no reason to use schematics in the design at all (though I'd
argue that a top-level schematic can show a design hierarchy very
nicely). You can replace your schematic with the equivalent in VHDL to
connect your modules together.

Regards,
Mark

What I mean by won't simulate is I can't get a waveform back with the
Xilinx ISE simulator once I have turned all my vhdl into symbols and
wired them in a schematic.

Once I use the create symbol command on the vhdl and then use the
symbol in a schematic it doesn't seem to allow me to run a simulation,
everything just goes unintialized

This is likely all just because I'm unexperienced with using
schematics. Has anyone else had this issue when translatting a vhdl to
symbol?

[email protected] wrote:
> What I mean by won't simulate is I can't get a waveform back with the
> Xilinx ISE simulator once I have turned all my vhdl into symbols and
> wired them in a schematic.

It's easier to "wire" the sub entities into
top.vhd with an instance like this:

uart_1: entity work.UART -- using default generic constants
port map (
clock => clk_s, -- [in]
reset => rst_s, -- [in]
address => address_s, -- [in]
writeData => writeData_s, -- [in]
write_stb => write_stb_s, -- [in]
readData => readData_s, -- [out]
read_stb => read_stb_s, -- [in]
serialIn => serialIn_s, -- [in]
serialOut => serialOut_s -- [out]
);


Then instance top into your testbench.

-- Mike Treseler

Sounds better than what I've been doing so far.

I'll give it a shot, hopefully it will do the trick and let me see the
output waveform.

Thank you

Keith