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  #1 (permalink)  
Old 03-16-2005, 08:06 PM
Preben Holm
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Default type states is std_logic_vector(4 downto 0);

Hi everyone,

why doesn't this synthesize:


architecture Behavioral of datacontroller is
type states is std_logic_vector(4 downto 0);
constant stateStart : states := "00001";
constant stateWait : states := "00010";
constant stateTrigger : states := "00100";
constant stateHold : states := "01000";
constant stateRead : states := "10000";

signal holdoff : std_logic;
signal holdoff_counter_enable, holdoff_counter_reset : std_logic;

component counter19bit
Port ( clk, ce, reset : in std_logic;
preset : in std_logic_vector(19 downto 0);
c : out std_logic;
q : out std_logic_vector(18 downto 0));
end component;
begin
[SNIP]


It's directly taken from the book "VHDL made easy".
I'm using Xilinx Webpack 6.3i!


Thanks
Preben Holm
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  #2 (permalink)  
Old 03-16-2005, 09:28 PM
KCL
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Default Re: type states is std_logic_vector(4 downto 0);

show more of your code because with this we couldn't help you so much, and
what are you error message??

"Preben Holm" <[email protected]> a écrit dans le message de news:
[email protected]
> Hi everyone,
>
> why doesn't this synthesize:
>
>
> architecture Behavioral of datacontroller is
> type states is std_logic_vector(4 downto 0);
> constant stateStart : states := "00001";
> constant stateWait : states := "00010";
> constant stateTrigger : states := "00100";
> constant stateHold : states := "01000";
> constant stateRead : states := "10000";
>
> signal holdoff : std_logic;
> signal holdoff_counter_enable, holdoff_counter_reset : std_logic;
>
> component counter19bit
> Port ( clk, ce, reset : in std_logic;
> preset : in std_logic_vector(19 downto 0);
> c : out std_logic;
> q : out std_logic_vector(18 downto 0));
> end component;
> begin
> [SNIP]
>
>
> It's directly taken from the book "VHDL made easy".
> I'm using Xilinx Webpack 6.3i!
>
>
> Thanks
> Preben Holm



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  #3 (permalink)  
Old 03-17-2005, 10:24 AM
Alan Fitch
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Posts: n/a
Default Re: type states is std_logic_vector(4 downto 0);

Preben Holm wrote:
> Hi everyone,
>
> why doesn't this synthesize:
>
>
> architecture Behavioral of datacontroller is
> type states is std_logic_vector(4 downto 0);
> constant stateStart : states := "00001";
> constant stateWait : states := "00010";
> constant stateTrigger : states := "00100";
> constant stateHold : states := "01000";
> constant stateRead : states := "10000";
>
> signal holdoff : std_logic;
> signal holdoff_counter_enable, holdoff_counter_reset : std_logic;
>
> component counter19bit
> Port ( clk, ce, reset : in std_logic;
> preset : in std_logic_vector(19 downto 0);
> c : out std_logic;
> q : out std_logic_vector(18 downto 0));
> end component;
> begin
> [SNIP]
>
>
> It's directly taken from the book "VHDL made easy".
> I'm using Xilinx Webpack 6.3i!
>
>

Are you sure? I would expect

subtype states is std_logic_vector(4 downto 0);

regards
Alan
--
Alan Fitch
Doulos Ltd
http://www.doulos.com
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