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Old 05-13-2006, 05:59 PM
Jack Daly
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Default Trouble understanding Synplicity timing report

I'm having a problem understanding a Synplicity timing report. For the
input ports of the design, the report gives column headings of 'port
name', 'falling user constraint', 'rising user constraint', 'arrival
time', 'required time', and 'slack'. The problem is, I can't make any
sense of what 'arrival time' and 'required time' are, and so I can't
work out how they arrived at the slack figure.

Here's an example for input port 'INPA', clocked by 'CLKA'. CLKA is
20ns. At the device pins, INPA has a setup of 8ns and a hold of 1ns
relative to CLKA, so this is how I constrained INPA:

define_input_delay {INPA} -rise 8 -fall 8 -min_rise -1 -min_fall -1
-ref {CLKA:r}

I think this is correct; the rise/fall times are relative to the
*next* clock edge, so in other words INPA will be available >= 8ns
before a clock edge, and will hold for >= 1ns after that clock edge.
This is what the timing report says:

Port clock cons(F) cons(R) AT RT SLACK
INPA CLKA (rising) 8.000 8.000 8.000 5.125 -2.875

So what does this mean? Why is the 'arrival time' always shown as
being equal to the setup constraint (it is in all the reports, and
even the picture in the docs shows this)?

This is what the manual says:

>Port Name Port name
>Reference Clock Source clock
>Falling User Constraint Specified falling input delay constraint
>Rising User Constraint Specified rising input delay constraint
>Arrival Time Clock latency - input delay constraint
>Required time Requested period - clock delay at destination -
> setup of destination
>Slack (max/min analysis) Required time - arrival time.

I haven't specified any latency on CLKA. My head is spinning - I'll be
eternally grateful to anyone who can explain this!

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Old 05-13-2006, 10:51 PM
Jack Daly
Posts: n/a
Default Re: Trouble understanding Synplicity timing report

On Sat, 13 May 2006 17:59:20 +0100, Jack Daly <[email protected]>

>Here's an example for input port 'INPA', clocked by 'CLKA'. CLKA is
>20ns. At the device pins, INPA has a setup of 8ns and a hold of 1ns
>relative to CLKA, so this is how I constrained INPA:
>define_input_delay {INPA} -rise 8 -fall 8 -min_rise -1 -min_fall -1
>-ref {CLKA:r}

It looks like I got the constraint wrong - define_input_delay seems to
specify the total delay from the previous clock edge to when the
signal is available at the port. This explains why the arrival time is
the same as the constraint.

I've spent hours going through the docs and the website, and I
eventually found this out by checking the documentation on
*Synopsys's* set_input_delay, which Synplicity says is (almost) the
same. This is bizarre - there's not one picture or timing diagram
describing this in the entire manual, and the text describing it was
written by someone who certainly didn't understand it. Has anyone got
any useful pointers to a proper explanation of Synplicity constraints?

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