FPGA Central

Hi,

I want to interrupt MicroBlaze with the falling edge of a output port
of my peripheral.

I have linked this signal to one of the inputs of the Intc controller.
I define the port as interrupt in the mpd file:

PORT rx_interrupt = "", DIR = OUT, EDGE = FALLING, SIGIS =
INTERRUPT, INTERRUPT_PRIORITY = HIGH

The problem comes out when I reset o programm the FPGA. Even if the
interrupt controller works fine during the execution of the program,
something (don't know what yet) generates an interrupt when the FPGA
is reseted.

I've checked the functional behaviour simulation and the output of
Intc controller (IRQ) is asserted a few clock cycles after the reset
signal is disasserted.

Does anybody know what can be the source of the problem?

Thanks in advance,

Arkaitz.