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Old 02-22-2010, 12:37 PM
Dek
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Default Triming timing constraints from pin ...

Hi all,

I'm working on a Virtex5 xc5vlx50 and in my design I need to use some
block ram. I generated the core with core generator, but when I
implement the design I got this warning during mapping:


WARNING:Pack:231 - trimming timing constraints from pin hit2/RAM1/BU2/
U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_init.ram/TR
UE_DP.SINGLE_PRIM36.TDP of frag REGCLKBL connected to power/ground net
hit2/RAM1/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/
v5_init.ram/TR UE_DP.SINGLE_PRIM36.TDP_REGCLKBL_tiesig

Does anyone knows what it mean and how can i fix it? I found nothing
neither on the xilinx site nor on the web

Thanks all

Bye

Dek
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Old 02-22-2010, 04:45 PM
austin
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Default Re: Triming timing constraints from pin ...

Dek,

It is a warning: you do not necessarily have to fix it.

The tools are telling you that a net to a constant (1=power, or
0=ground) had its timing constraint removed (ignored).

That is a perfectly OK thing to do.

It is up to you to read each warning, and check out what it means.

This one is easy, let it go.

Austin
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  #3 (permalink)  
Old 02-23-2010, 03:20 PM
Dek
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Default Re: Triming timing constraints from pin ...

On 22 Feb, 16:45, austin <[email protected]> wrote:
> Dek,
>
> It is a warning: *you do not necessarily have to fix it.
>
> The tools are telling you that a net to a constant (1=power, or
> 0=ground) had its timing constraint removed (ignored).
>
> That is a perfectly OK thing to do.
>
> It is up to you to read each warning, and check out what it means.
>
> This one is easy, let it go.
>
> Austin


Hi Austin

Thanks for the reply; the point is that I have a project that uses
some block ram; In functional simulation everything works fine, when I
do synthesys and place and route I got no errors, no timing related
problems, and just 2 kind of warnings:

Xst:2211: ... line 130: Instantiating black box module <ram_128>
( see http://groups.google.it/group/comp.l...2ad29181e18171
)

and

Pack:231 - trimming timing constraints from pin as described above

If I try to do a post layout simulation of this design with Modelsim;
I got this warning:

# ** Warning: /X_FF HOLD Low VIOLATION ON I WITH RESPECT TO CLK;
# Expected := 0.195 ns; Observed := 0.006 ns; At : 191.527 ns
# Time: 191527 ps Iteration: 1 Instance: /newdaedalus_tb/top/
control_cnt_0

and the design does not behave like in functional analysis. I also
implemented the bitfile on real hardware but it doesn't work. That's
why I was asking about that warning, because I really can't get where
the problem could be...

I'm using the block ram @ 40 MHz, but it shouldn't be a problem,
right?

Thanks

Bye

Dek
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