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  #1 (permalink)  
Old 11-30-2007, 11:12 PM
tang
Guest
 
Posts: n/a
Default Traffic Light with counter

hey guys i hope u can help me out... i want to design a simple traffic
light controller according to the 4 states shown in the code below. my
only problem is that my signal state_reg is not changing form one
state to another. this is because the counter i included in the the
code as a process is not working. green to yellow time wait is 30 sec
and yellow to red is 5 sec. my clock period will be 5 sec. so can
anyone help me out

----------------------------------------------------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity TLC is
port(
clk,reset, sa, sb:in std_logic;
Ga, Ya, Ra, Gb, Yb, Rbut std_logic
);
end TLC;

architecture Behavioral of TLC is

type state_type is (a, b, c, d);
signal state_reg, state_next: state_type;
signal Pre_Q, Q: std_logic_vector(3 downto 0);
signal count, clear: std_logic;

begin

-- behavior describe the counter
process(clk, count, clear)
begin
if (clear = '0') then
Pre_Q <= Pre_Q - Pre_Q;
elsif (clk='1' and clk'event) then
if (count = '1') then
Pre_Q <= Pre_Q + 1;
end if;
end if;
Q <= Pre_Q;
end process;

-- state register

process(clk,reset)
begin
if(reset='0') then
state_reg <= a;
elsif (clk'event and clk='1') then
state_reg <= state_next;
end if;
end process;

-- next state logic

process(state_reg,Q,sa,sb)
begin

case state_reg is
when a =>
if(sa = '1' and sb = '0')then
state_next <= a;
elsif (sa = '0' and sb = '1') then
count <= '1';
if(Q = "0110") then
state_next <= b;
end if;
end if;

when b =>

if(Q = "0111") then
state_next <= c;
count <= '0';
elsif(sa = '1') then
state_next <= b;
end if;

when c =>
if(sa = '0' and sb = '1') then
state_next <= c;
elsif (sa = '1' and sb ='0') then
clear <= '0';
count <= '1';
if(Q = "0110") then
state_next <= d;

end if;
end if;

when d =>

if(Q = "0111") then
state_next <= a;
count <= '0';
elsif(sb = '1') then
state_next <= d;
end if;
end case;
end process;

process (state_reg)
begin
Ga <= '1'; Ya <= '0'; Ra <= '0';
Gb <= '0'; Yb <= '0'; Rb <= '1';

case state_reg is
when a =>
when b =>
Ga <= '0';
Ya <= '1';

when c =>
Ya <= '0';
Ra <= '1';
Gb <= '1';

when d =>
Gb <= '0';
Yb <= '1';

end case;

end process;

end Behavioral;
--------------------------------------------------------------------------------------------------------------------------------------------------------
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  #2 (permalink)  
Old 11-30-2007, 11:57 PM
Dave
Guest
 
Posts: n/a
Default Re: Traffic Light with counter

On Nov 30, 5:12 pm, tang <[email protected]> wrote:
> hey guys i hope u can help me out... i want to design a simple traffic
> light controller according to the 4 states shown in the code below. my
> only problem is that my signal state_reg is not changing form one
> state to another. this is because the counter i included in the the
> code as a process is not working. green to yellow time wait is 30 sec
> and yellow to red is 5 sec. my clock period will be 5 sec. so can
> anyone help me out
>
> ------------------------------------------------------------------------------------------------------------------------------------------------------------
> library ieee;
> use ieee.std_logic_1164.all;
> use ieee.std_logic_arith.all;
> use IEEE.std_logic_unsigned.all;
>
> entity TLC is
> port(
> clk,reset, sa, sb:in std_logic;
> Ga, Ya, Ra, Gb, Yb, Rbut std_logic
> );
> end TLC;
>
> architecture Behavioral of TLC is
>
> type state_type is (a, b, c, d);
> signal state_reg, state_next: state_type;
> signal Pre_Q, Q: std_logic_vector(3 downto 0);
> signal count, clear: std_logic;
>
> begin
>
> -- behavior describe the counter
> process(clk, count, clear)
> begin
> if (clear = '0') then
> Pre_Q <= Pre_Q - Pre_Q;
> elsif (clk='1' and clk'event) then
> if (count = '1') then
> Pre_Q <= Pre_Q + 1;
> end if;
> end if;
> Q <= Pre_Q;
> end process;
>
> -- state register
>
> process(clk,reset)
> begin
> if(reset='0') then
> state_reg <= a;
> elsif (clk'event and clk='1') then
> state_reg <= state_next;
> end if;
> end process;
>
> -- next state logic
>
> process(state_reg,Q,sa,sb)
> begin
>
> case state_reg is
> when a =>
> if(sa = '1' and sb = '0')then
> state_next <= a;
> elsif (sa = '0' and sb = '1') then
> count <= '1';
> if(Q = "0110") then
> state_next <= b;
> end if;
> end if;
>
> when b =>
>
> if(Q = "0111") then
> state_next <= c;
> count <= '0';
> elsif(sa = '1') then
> state_next <= b;
> end if;
>
> when c =>
> if(sa = '0' and sb = '1') then
> state_next <= c;
> elsif (sa = '1' and sb ='0') then
> clear <= '0';
> count <= '1';
> if(Q = "0110") then
> state_next <= d;
>
> end if;
> end if;
>
> when d =>
>
> if(Q = "0111") then
> state_next <= a;
> count <= '0';
> elsif(sb = '1') then
> state_next <= d;
> end if;
> end case;
> end process;
>
> process (state_reg)
> begin
> Ga <= '1'; Ya <= '0'; Ra <= '0';
> Gb <= '0'; Yb <= '0'; Rb <= '1';
>
> case state_reg is
> when a =>
> when b =>
> Ga <= '0';
> Ya <= '1';
>
> when c =>
> Ya <= '0';
> Ra <= '1';
> Gb <= '1';
>
> when d =>
> Gb <= '0';
> Yb <= '1';
>
> end case;
>
> end process;
>
> end Behavioral;
> ----------------------------------------------------------------------------------------------------------------------------------------------------------


First, I would stongly suggest you use numeric_std instead of
std_logic_arith, especially when you're learning, since it's the
accepted standard. Next, remember that at the start of simulation, all
of your std_logic signal and output values are 'U', or unspecified.
Any operation you perform where one of the operands is 'U' will most
likely return 'U', so at some point you've got to give them a concrete
value if you want anything to happen.

Also, in a case statement, if you want to cover multiple cases, use
"when a | b =>", not "when a => when b =>". That's the way it's done
in C, not VHDL.

These aren't all the problems, but hopefully this will set you on the
right track.
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  #3 (permalink)  
Old 12-01-2007, 03:16 AM
Symon
Guest
 
Posts: n/a
Default Re: Traffic Light with counter

"tang" <[email protected]> wrote in message
news:[email protected]m...
> hey guys i hope u can help me out... i want to design a simple traffic
> light controller according to the 4 states shown in the code below. my
> only problem is that my signal state_reg is not changing form one
> state to another. this is because the counter i included in the the
> code as a process is not working. green to yellow time wait is 30 sec
> and yellow to red is 5 sec. my clock period will be 5 sec. so can
> anyone help me out
>

Hey tang,
You should try comp.lang.vhdl . There are a bunch of blokes over there who
_really_ know how sensitivity lists work. Ask for Mike xor Jonathan orif
Jim. They're among the best at homework. Tell them I sent you.
HTH., Syms.
p.s. These days, 'traffic light vhdl' is at 159000 Google hits. Adding
lumberjack to the search gets you down to a more sensible 39. Only two worse
than adding omg ponies. (Thanks to Ben J. for that insight!) Be sure to turn
off 'safe search'.


Reply With Quote
  #4 (permalink)  
Old 12-01-2007, 10:07 AM
Jonathan Bromley
Guest
 
Posts: n/a
Default Re: Traffic Light with counter

On Sat, 1 Dec 2007 02:16:06 -0000, Symon wrote:

>You should try comp.lang.vhdl . There are a bunch of blokes over there who
>_really_ know how sensitivity lists work. Ask for Mike xor Jonathan orif
>Jim. They're among the best at homework. Tell them I sent you.
>HTH., Syms.


Symon, you are A Very Bad Person. I can think of nations less
tolerant and inclusive than ours where this sort of incitement
to technical hatred could get you a stiff sentence (something
along the lines of "This sentence is inflexible"?).

>p.s. These days, 'traffic light vhdl' is at 159000 Google hits. Adding
>lumberjack to the search gets you down to a more sensible 39. Only two worse
>than adding omg ponies.


[chokes on breakfast toast] Brilliant!
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
[email protected]
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Reply With Quote
  #5 (permalink)  
Old 12-01-2007, 10:59 AM
John Adair
Guest
 
Posts: n/a
Default Re: Traffic Light with counter

There are a large number of ways you could do this. Personally I'm not
a get fan of next state, current state, style you use but it does have
it's followers.

Staying with what you have I would check the asychronous
(combinatorial) processes have complete sensativity lists. Your
clocked processes I would make sure all statements lie with the clock
and reset statements.

Personally I would have a counter that reloaded with values linked to
the transitions of the state machine and taking a count value relevant
to the state being entered. The counter then counts down to zero and
then the next state transition. If you make your counter integer type
you don't need extra numerical type libraries.

John Adair
Enterpoint Ltd. - Home of Craignells The obsolete DIL solution.

On 30 Nov, 22:12, tang <[email protected]> wrote:
> hey guys i hope u can help me out... i want to design a simple traffic
> light controller according to the 4 states shown in the code below. my
> only problem is that my signal state_reg is not changing form one
> state to another. this is because the counter i included in the the
> code as a process is not working. green to yellow time wait is 30 sec
> and yellow to red is 5 sec. my clock period will be 5 sec. so can
> anyone help me out
>
> ------------------------------------------------------------------------------------------------------------------------------------------------------------
> library ieee;
> use ieee.std_logic_1164.all;
> use ieee.std_logic_arith.all;
> use IEEE.std_logic_unsigned.all;
>
> entity TLC is
> port(
> clk,reset, sa, sb:in std_logic;
> Ga, Ya, Ra, Gb, Yb, Rbut std_logic
> );
> end TLC;
>
> architecture Behavioral of TLC is
>
> type state_type is (a, b, c, d);
> signal state_reg, state_next: state_type;
> signal Pre_Q, Q: std_logic_vector(3 downto 0);
> signal count, clear: std_logic;
>
> begin
>
> -- behavior describe the counter
> process(clk, count, clear)
> begin
> if (clear = '0') then
> Pre_Q <= Pre_Q - Pre_Q;
> elsif (clk='1' and clk'event) then
> if (count = '1') then
> Pre_Q <= Pre_Q + 1;
> end if;
> end if;
> Q <= Pre_Q;
> end process;
>
> -- state register
>
> process(clk,reset)
> begin
> if(reset='0') then
> state_reg <= a;
> elsif (clk'event and clk='1') then
> state_reg <= state_next;
> end if;
> end process;
>
> -- next state logic
>
> process(state_reg,Q,sa,sb)
> begin
>
> case state_reg is
> when a =>
> if(sa = '1' and sb = '0')then
> state_next <= a;
> elsif (sa = '0' and sb = '1') then
> count <= '1';
> if(Q = "0110") then
> state_next <= b;
> end if;
> end if;
>
> when b =>
>
> if(Q = "0111") then
> state_next <= c;
> count <= '0';
> elsif(sa = '1') then
> state_next <= b;
> end if;
>
> when c =>
> if(sa = '0' and sb = '1') then
> state_next <= c;
> elsif (sa = '1' and sb ='0') then
> clear <= '0';
> count <= '1';
> if(Q = "0110") then
> state_next <= d;
>
> end if;
> end if;
>
> when d =>
>
> if(Q = "0111") then
> state_next <= a;
> count <= '0';
> elsif(sb = '1') then
> state_next <= d;
> end if;
> end case;
> end process;
>
> process (state_reg)
> begin
> Ga <= '1'; Ya <= '0'; Ra <= '0';
> Gb <= '0'; Yb <= '0'; Rb <= '1';
>
> case state_reg is
> when a =>
> when b =>
> Ga <= '0';
> Ya <= '1';
>
> when c =>
> Ya <= '0';
> Ra <= '1';
> Gb <= '1';
>
> when d =>
> Gb <= '0';
> Yb <= '1';
>
> end case;
>
> end process;
>
> end Behavioral;
> ----------------------------------------------------------------------------------------------------------------------------------------------------------


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  #6 (permalink)  
Old 12-01-2007, 05:49 PM
tang
Guest
 
Posts: n/a
Default Re: Traffic Light with counter

On Dec 1, 1:59 am, John Adair <[email protected]> wrote:
> There are a large number of ways you could do this. Personally I'm not
> a get fan of next state, current state, style you use but it does have
> it's followers.
>
> Staying with what you have I would check the asychronous
> (combinatorial) processes have complete sensativity lists. Your
> clocked processes I would make sure all statements lie with the clock
> and reset statements.
>
> Personally I would have a counter that reloaded with values linked to
> the transitions of the state machine and taking a count value relevant
> to the state being entered. The counter then counts down to zero and
> then the next state transition. If you make your counter integer type
> you don't need extra numerical type libraries.
>
> John Adair
> Enterpoint Ltd. - Home of Craignells The obsolete DIL solution.
>
> On 30 Nov, 22:12, tang <[email protected]> wrote:
>
>
>
>
>
> > hey guys i hope u can help me out... i want to design a simple traffic
> > light controller according to the 4 states shown in the code below. my
> > only problem is that my signal state_reg is not changing form one
> > state to another. this is because the counter i included in the the
> > code as a process is not working. green to yellow time wait is 30 sec
> > and yellow to red is 5 sec. my clock period will be 5 sec. so can
> > anyone help me out

>
> > ------------------------------------------------------------------------------------------------------------------------------------------------------------
> > library ieee;
> > use ieee.std_logic_1164.all;
> > use ieee.std_logic_arith.all;
> > use IEEE.std_logic_unsigned.all;

>
> > entity TLC is
> > port(
> > clk,reset, sa, sb:in std_logic;
> > Ga, Ya, Ra, Gb, Yb, Rbut std_logic
> > );
> > end TLC;

>
> > architecture Behavioral of TLC is

>
> > type state_type is (a, b, c, d);
> > signal state_reg, state_next: state_type;
> > signal Pre_Q, Q: std_logic_vector(3 downto 0);
> > signal count, clear: std_logic;

>
> > begin

>
> > -- behavior describe the counter
> > process(clk, count, clear)
> > begin
> > if (clear = '0') then
> > Pre_Q <= Pre_Q - Pre_Q;
> > elsif (clk='1' and clk'event) then
> > if (count = '1') then
> > Pre_Q <= Pre_Q + 1;
> > end if;
> > end if;
> > Q <= Pre_Q;
> > end process;

>
> > -- state register

>
> > process(clk,reset)
> > begin
> > if(reset='0') then
> > state_reg <= a;
> > elsif (clk'event and clk='1') then
> > state_reg <= state_next;
> > end if;
> > end process;

>
> > -- next state logic

>
> > process(state_reg,Q,sa,sb)
> > begin

>
> > case state_reg is
> > when a =>
> > if(sa = '1' and sb = '0')then
> > state_next <= a;
> > elsif (sa = '0' and sb = '1') then
> > count <= '1';
> > if(Q = "0110") then
> > state_next <= b;
> > end if;
> > end if;

>
> > when b =>

>
> > if(Q = "0111") then
> > state_next <= c;
> > count <= '0';
> > elsif(sa = '1') then
> > state_next <= b;
> > end if;

>
> > when c =>
> > if(sa = '0' and sb = '1') then
> > state_next <= c;
> > elsif (sa = '1' and sb ='0') then
> > clear <= '0';
> > count <= '1';
> > if(Q = "0110") then
> > state_next <= d;

>
> > end if;
> > end if;

>
> > when d =>

>
> > if(Q = "0111") then
> > state_next <= a;
> > count <= '0';
> > elsif(sb = '1') then
> > state_next <= d;
> > end if;
> > end case;
> > end process;

>
> > process (state_reg)
> > begin
> > Ga <= '1'; Ya <= '0'; Ra <= '0';
> > Gb <= '0'; Yb <= '0'; Rb <= '1';

>
> > case state_reg is
> > when a =>
> > when b =>
> > Ga <= '0';
> > Ya <= '1';

>
> > when c =>
> > Ya <= '0';
> > Ra <= '1';
> > Gb <= '1';

>
> > when d =>
> > Gb <= '0';
> > Yb <= '1';

>
> > end case;

>
> > end process;

>
> > end Behavioral;
> > ----------------------------------------------------------------------------------------------------------------------------------------------------------


Thanx for the solution. I was also thinking about making counter
integer. Can you please elaborate on that? will it be like adding for
loop till count reach to desired value and then perform the
transition?
thanx again
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  #7 (permalink)  
Old 12-01-2007, 05:55 PM
tang
Guest
 
Posts: n/a
Default Re: Traffic Light with counter

On Nov 30, 6:16 pm, "Symon" <[email protected]> wrote:
> "tang" <[email protected]> wrote in message
>
> news:[email protected]m...> hey guys i hope u can help me out... i want to design a simple traffic
> > light controller according to the 4 states shown in the code below. my
> > only problem is that my signal state_reg is not changing form one
> > state to another. this is because the counter i included in the the
> > code as a process is not working. green to yellow time wait is 30 sec
> > and yellow to red is 5 sec. my clock period will be 5 sec. so can
> > anyone help me out

>
> Hey tang,
> You should try comp.lang.vhdl . There are a bunch of blokes over there who
> _really_ know how sensitivity lists work. Ask for Mike xor Jonathan orif
> Jim. They're among the best at homework. Tell them I sent you.
> HTH., Syms.
> p.s. These days, 'traffic light vhdl' is at 159000 Google hits. Adding
> lumberjack to the search gets you down to a more sensible 39. Only two worse
> than adding omg ponies. (Thanks to Ben J. for that insight!) Be sure to turn
> off 'safe search'.


thanx for the reply...
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  #8 (permalink)  
Old 12-01-2007, 08:33 PM
Mike Treseler
Guest
 
Posts: n/a
Default Re: Traffic Light with counter

Symon wrote:

> p.s. These days, 'traffic light vhdl' is at 159000 Google hits. Adding
> lumberjack to the search gets you down to a more sensible 39.


farm_traffic takes it down to one.
http://groups.google.com/groups/search?q=farm_traffic

-- Mike Treseler

Reply With Quote
  #9 (permalink)  
Old 12-01-2007, 11:23 PM
Jonathan Bromley
Guest
 
Posts: n/a
Default Re: Traffic Light with counter

On Sat, 01 Dec 2007 11:33:23 -0800, Mike Treseler wrote:

>farm_traffic takes it down to one.
>http://groups.google.com/groups/search?q=farm_traffic


Sorry Mike, it's two now - and this post will make it three :-)
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
[email protected]
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Reply With Quote
  #10 (permalink)  
Old 12-02-2007, 12:32 AM
KJ
Guest
 
Posts: n/a
Default Re: Traffic Light with counter


"Jonathan Bromley" <[email protected]> wrote in message
news:[email protected]
> On Sat, 01 Dec 2007 11:33:23 -0800, Mike Treseler wrote:
>
>>farm_traffic takes it down to one.
>>http://groups.google.com/groups/search?q=farm_traffic

>
> Sorry Mike, it's two now - and this post will make it three :-)
> --
> Jonathan Bromley, Consultant
>


My gosh, you're right....it just keeps a growin, will it never end????

Can get it back down to 1 though by filtering out anything with the
following words

mike treseler wrote jonathan bromley

http://groups.google.com/groups?as_q...=2007&safe=off

KJ


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  #11 (permalink)  
Old 12-02-2007, 10:25 AM
Symon
Guest
 
Posts: n/a
Default Re: Traffic Light with counter

"KJ" <[email protected]> writted in message
news:[email protected]
>
> "Bronathan Jimley" <[email protected]> writted in message
> news:[email protected]
>> On Sat, 01 Dec 2007 11:33:23 -0800, Trick Misseller writted:
>>
>>>farm_traffic takes it down to one.
>>>http://groups.google.com/groups/search?q=farm_traffic

>>
>> Sorry Trick, it's two now - and this post will make it three :-)
>> --
>> Bronathan Jimley, Consultant
>>

>
> My gosh, you're right....it just keeps a growin, will it never end????
>
> Can get it back down to 1 though by filtering out anything with the
> following words
>
> Trick Misseller writted Bronathan Jimley
>
> http://groups.google.com/groups?as_q...nathan+Jimley&
>
> KJ
>

Not now.
Myss.



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  #12 (permalink)  
Old 12-02-2007, 11:33 PM
Marlboro
Guest
 
Posts: n/a
Default Re: Traffic Light with counter

On Dec 1, 10:49 am, tang <[email protected]> wrote:
> On Dec 1, 1:59 am, John Adair <[email protected]> wrote:
>
>
>
>
>
> > There are a large number of ways you could do this. Personally I'm not
> > a get fan of next state, current state, style you use but it does have
> > it's followers.

>
> > Staying with what you have I would check the asychronous
> > (combinatorial) processes have complete sensativity lists. Your
> > clocked processes I would make sure all statements lie with the clock
> > and reset statements.

>
> > Personally I would have a counter that reloaded with values linked to
> > the transitions of the state machine and taking a count value relevant
> > to the state being entered. The counter then counts down to zero and
> > then the next state transition. If you make your counter integer type
> > you don't need extra numerical type libraries.

>
> > John Adair
> > Enterpoint Ltd. - Home of Craignells The obsolete DIL solution.

>
> > On 30 Nov, 22:12, tang <[email protected]> wrote:

>
> > > hey guys i hope u can help me out... i want to design a simple traffic
> > > light controller according to the 4 states shown in the code below. my
> > > only problem is that my signal state_reg is not changing form one
> > > state to another. this is because the counter i included in the the
> > > code as a process is not working. green to yellow time wait is 30 sec
> > > and yellow to red is 5 sec. my clock period will be 5 sec. so can
> > > anyone help me out

>
> > > --------------------------------------------------------------------------------------------------------------------------------------------------------------
> > > library ieee;
> > > use ieee.std_logic_1164.all;
> > > use ieee.std_logic_arith.all;
> > > use IEEE.std_logic_unsigned.all;

>
> > > entity TLC is
> > > port(
> > > clk,reset, sa, sb:in std_logic;
> > > Ga, Ya, Ra, Gb, Yb, Rbut std_logic
> > > );
> > > end TLC;

>
> > > architecture Behavioral of TLC is

>
> > > type state_type is (a, b, c, d);
> > > signal state_reg, state_next: state_type;
> > > signal Pre_Q, Q: std_logic_vector(3 downto 0);
> > > signal count, clear: std_logic;

>
> > > begin

>
> > > -- behavior describe the counter
> > > process(clk, count, clear)
> > > begin
> > > if (clear = '0') then
> > > Pre_Q <= Pre_Q - Pre_Q;
> > > elsif (clk='1' and clk'event) then
> > > if (count = '1') then
> > > Pre_Q <= Pre_Q + 1;
> > > end if;
> > > end if;
> > > Q <= Pre_Q;
> > > end process;

>
> > > -- state register

>
> > > process(clk,reset)
> > > begin
> > > if(reset='0') then
> > > state_reg <= a;
> > > elsif (clk'event and clk='1') then
> > > state_reg <= state_next;
> > > end if;
> > > end process;

>
> > > -- next state logic

>
> > > process(state_reg,Q,sa,sb)
> > > begin

>
> > > case state_reg is
> > > when a =>
> > > if(sa = '1' and sb = '0')then
> > > state_next <= a;
> > > elsif (sa = '0' and sb = '1') then
> > > count <= '1';
> > > if(Q = "0110") then
> > > state_next <= b;
> > > end if;
> > > end if;

>
> > > when b =>

>
> > > if(Q = "0111") then
> > > state_next <= c;
> > > count <= '0';
> > > elsif(sa = '1') then
> > > state_next <= b;
> > > end if;

>
> > > when c =>
> > > if(sa = '0' and sb = '1') then
> > > state_next <= c;
> > > elsif (sa = '1' and sb ='0') then
> > > clear <= '0';
> > > count <= '1';
> > > if(Q = "0110") then
> > > state_next <= d;

>
> > > end if;
> > > end if;

>
> > > when d =>

>
> > > if(Q = "0111") then
> > > state_next <= a;
> > > count <= '0';
> > > elsif(sb = '1') then
> > > state_next <= d;
> > > end if;
> > > end case;
> > > end process;

>
> > > process (state_reg)
> > > begin
> > > Ga <= '1'; Ya <= '0'; Ra <= '0';
> > > Gb <= '0'; Yb <= '0'; Rb <= '1';

>
> > > case state_reg is
> > > when a =>
> > > when b =>
> > > Ga <= '0';
> > > Ya <= '1';

>
> > > when c =>
> > > Ya <= '0';
> > > Ra <= '1';
> > > Gb <= '1';

>
> > > when d =>
> > > Gb <= '0';
> > > Yb <= '1';

>
> > > end case;

>
> > > end process;

>
> > > end Behavioral;
> > > ------------------------------------------------------------------------------------------------------------------------------------------------------------

>
> Thanx for the solution. I was also thinking about making counter
> integer. Can you please elaborate on that? will it be like adding for
> loop till count reach to desired value and then perform the
> transition?
> thanx again- Hide quoted text -
>
> - Show quoted text -


How many mega herzts will your red light controller run at ?
Reply With Quote
  #13 (permalink)  
Old 12-03-2007, 03:35 PM
John Adair
Guest
 
Posts: n/a
Default Re: Traffic Light with counter

Start by defining a state machine that has all the states you need and
outline the transitions you need qualified with counter. An example (NOT
SYNTAX CHECKED) of 4 states below.

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY TRAFFIC IS
PORT( CLOCK : IN STD_LOGIC;
RESET : IN STD_LOGIC;

OP1 : OUT STD_LOGIC;
OP2 : OUT STD_LOGIC);
END TRAFFIC;

ARCHITECTURE A0 OF TRAFFIC IS

SIGNAL COUNTER : INTEGER RANGE 0 TO 10000000;

TYPE SM_TRAFFIC_TYPE IS( SM_TRAFFIC_IDLE ,
SM_TRAFFIC_OP1_ON ,
SM_TRAFFIC_OP2_ON ,
SM_TRAFFIC_OP1_OP2_ON );

SIGNAL SM_TRAFFIC : SM_TRAFFIC_TYPE;

BEGIN

TR1 : PROCESS(RESET,CLOCK)
BEGIN
IF (RESET = '1') THEN
SM_TRAFFIC <= SM_TRAFFIC_IDLE;
COUNTER <= 1000;
OP1 <= '0';
OP2 <= '0';

ELSIF (CLOCK'EVENT AND CLOCK='1') THEN
CASE SM_TRAFFIC IS
WHEN SM_TRAFFIC_IDLE =>
SM_TRAFFIC <= SM_TRAFFIC_OP1_ON;
COUNTER <= 1000;
OP1 <= '1';
OP2 <= '0';
--STAY GERE 1000 CLOCKS
WHEN SM_TRAFFIC_OP1_ON =>
IF (COUNTER = 0) THEN
SM_TRAFFIC <= SM_TRAFFIC_OP2_ON;
COUNTER <= 5000000;
OP1 <= '0';
OP2 <= '1';
ELSE
SM_TRAFFIC <= SM_TRAFFIC_OP1_ON;
COUNTER <= COUNTER - 1;
OP1 <= '1';
OP2 <= '0';
END IF;
--STAY HERE 5000000 CLOCKS
WHEN SM_TRAFFIC_OP2_ON =>
IF (COUNTER = 0) THEN
SM_TRAFFIC <= SM_TRAFFIC_OP1_OP2_ON;
COUNTER <= 4000000;
OP1 <= '1';
OP2 <= '1';
ELSE
SM_TRAFFIC <= SM_TRAFFIC_OP2_ON;
COUNTER <= COUNTER - 1;
OP1 <= '0';
OP2 <= '1';
END IF;
--SM_TRAFFIC_OP1_OP2_ON
--STAY HERE 4000000 CLOCKS
WHEN OTHERS =>
IF (COUNTER = 0) THEN
SM_TRAFFIC <= SM_TRAFFIC_OP1_ON;
COUNTER <= 1000;
OP1 <= '1';
OP2 <= '0';
ELSE
SM_TRAFFIC <= SM_TRAFFIC_OP2_ON;
COUNTER <= COUNTER - 1;
OP1 <= '0';
OP2 <= '0';
END IF;
END CASE;
END IF;
END PROCESS TR1;

END A0 ;

John Adair
Enterpoint Ltd.
Home of Drigmorn1. The hobby FPGA Development Board.

"tang" <[email protected]> wrote in message
news:[email protected]m...
> On Dec 1, 1:59 am, John Adair <[email protected]> wrote:
>> There are a large number of ways you could do this. Personally I'm not
>> a get fan of next state, current state, style you use but it does have
>> it's followers.
>>
>> Staying with what you have I would check the asychronous
>> (combinatorial) processes have complete sensativity lists. Your
>> clocked processes I would make sure all statements lie with the clock
>> and reset statements.
>>
>> Personally I would have a counter that reloaded with values linked to
>> the transitions of the state machine and taking a count value relevant
>> to the state being entered. The counter then counts down to zero and
>> then the next state transition. If you make your counter integer type
>> you don't need extra numerical type libraries.
>>
>> John Adair
>> Enterpoint Ltd. - Home of Craignells The obsolete DIL solution.
>>
>> On 30 Nov, 22:12, tang <[email protected]> wrote:
>>
>>
>>
>>
>>
>> > hey guys i hope u can help me out... i want to design a simple traffic
>> > light controller according to the 4 states shown in the code below. my
>> > only problem is that my signal state_reg is not changing form one
>> > state to another. this is because the counter i included in the the
>> > code as a process is not working. green to yellow time wait is 30 sec
>> > and yellow to red is 5 sec. my clock period will be 5 sec. so can
>> > anyone help me out

>>
>> > ------------------------------------------------------------------------------------------------------------------------------------------------------------
>> > library ieee;
>> > use ieee.std_logic_1164.all;
>> > use ieee.std_logic_arith.all;
>> > use IEEE.std_logic_unsigned.all;

>>
>> > entity TLC is
>> > port(
>> > clk,reset, sa, sb:in std_logic;
>> > Ga, Ya, Ra, Gb, Yb, Rbut std_logic
>> > );
>> > end TLC;

>>
>> > architecture Behavioral of TLC is

>>
>> > type state_type is (a, b, c, d);
>> > signal state_reg, state_next: state_type;
>> > signal Pre_Q, Q: std_logic_vector(3 downto 0);
>> > signal count, clear: std_logic;

>>
>> > begin

>>
>> > -- behavior describe the counter
>> > process(clk, count, clear)
>> > begin
>> > if (clear = '0') then
>> > Pre_Q <= Pre_Q - Pre_Q;
>> > elsif (clk='1' and clk'event) then
>> > if (count = '1') then
>> > Pre_Q <= Pre_Q + 1;
>> > end if;
>> > end if;
>> > Q <= Pre_Q;
>> > end process;

>>
>> > -- state register

>>
>> > process(clk,reset)
>> > begin
>> > if(reset='0') then
>> > state_reg <= a;
>> > elsif (clk'event and clk='1') then
>> > state_reg <= state_next;
>> > end if;
>> > end process;

>>
>> > -- next state logic

>>
>> > process(state_reg,Q,sa,sb)
>> > begin

>>
>> > case state_reg is
>> > when a =>
>> > if(sa = '1' and sb = '0')then
>> > state_next <= a;
>> > elsif (sa = '0' and sb = '1') then
>> > count <= '1';
>> > if(Q = "0110") then
>> > state_next <= b;
>> > end if;
>> > end if;

>>
>> > when b =>

>>
>> > if(Q = "0111") then
>> > state_next <= c;
>> > count <= '0';
>> > elsif(sa = '1') then
>> > state_next <= b;
>> > end if;

>>
>> > when c =>
>> > if(sa = '0' and sb = '1') then
>> > state_next <= c;
>> > elsif (sa = '1' and sb ='0') then
>> > clear <= '0';
>> > count <= '1';
>> > if(Q = "0110") then
>> > state_next <= d;

>>
>> > end if;
>> > end if;

>>
>> > when d =>

>>
>> > if(Q = "0111") then
>> > state_next <= a;
>> > count <= '0';
>> > elsif(sb = '1') then
>> > state_next <= d;
>> > end if;
>> > end case;
>> > end process;

>>
>> > process (state_reg)
>> > begin
>> > Ga <= '1'; Ya <= '0'; Ra <= '0';
>> > Gb <= '0'; Yb <= '0'; Rb <= '1';

>>
>> > case state_reg is
>> > when a =>
>> > when b =>
>> > Ga <= '0';
>> > Ya <= '1';

>>
>> > when c =>
>> > Ya <= '0';
>> > Ra <= '1';
>> > Gb <= '1';

>>
>> > when d =>
>> > Gb <= '0';
>> > Yb <= '1';

>>
>> > end case;

>>
>> > end process;

>>
>> > end Behavioral;
>> > ----------------------------------------------------------------------------------------------------------------------------------------------------------

>
> Thanx for the solution. I was also thinking about making counter
> integer. Can you please elaborate on that? will it be like adding for
> loop till count reach to desired value and then perform the
> transition?
> thanx again



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