FPGA Central

What are your views on http://scratchpad.wikia.com/wiki/TileraMulticore
as a replacement for FPGA's ?

http://www.tilera.com/solutions/digital_baseband.php

The current architecture for base stations fall short of delivering
the performance, the low latency and the flexibility customers need.
To meet the requirements, wireless equipment providers design complex
systems with FPGA, ASIC, DSP and processors with each component
requiring special tools in a customized development environment. This
leads to a long development cycle, sometimes years, before
applications can be productized. Changes in standards also impact
providers because such systems are inflexible-upgrades can be a slow
and expensive process.

What providers seek is an uncomplicated, well-designed, architecture
that yields good performance. Tilera's processors provide a low
latency single solution that integrates many functions seamlessly in a
single processor and uses C/C++ to program their applications with
industry standard tools. The familiar tools enable customers to
preserve their software investments, replace a number of disparate
programming methodologies with one standard programming environment,
and gain the flexibility they need to support evolving protocols and
ever-increasing demands for service

mentari wrote:
> What are your views on http://scratchpad.wikia.com/wiki/TileraMulticore
> as a replacement for FPGA's ?

http://groups.google.com/group/comp....a7f70929b2f1e2

Last I checked there was little info about price or availability.

-Jeff

On 7 Nov, 10:25, mentari <[email protected]> wrote:
> What are your views onhttp://scratchpad.wikia.com/wiki/TileraMulticore
> as a replacement for FPGA's ?
>
> http://www.tilera.com/solutions/digital_baseband.php
>
> The current architecture for base stations fall short of delivering
> the performance, the low latency and the flexibility customers need.
> To meet the requirements, wireless equipment providers design complex
> systems with FPGA, ASIC, DSP and processors with each component
> requiring special tools in a customized development environment. This
> leads to a long development cycle, sometimes years, before
> applications can be productized. Changes in standards also impact
> providers because such systems are inflexible-upgrades can be a slow
> and expensive process.
>
> What providers seek is an uncomplicated, well-designed, architecture
> that yields good performance. Tilera's processors provide a low
> latency single solution that integrates many functions seamlessly in a
> single processor and uses C/C++ to program their applications with
> industry standard tools. The familiar tools enable customers to
> preserve their software investments, replace a number of disparate
> programming methodologies with one standard programming environment,
> and gain the flexibility they need to support evolving protocols and
> ever-increasing demands for service

XMOS chips are intended to replace FPGAs in many applications, and are
available now:

http://www.xmos.com

Leon

On 7 nov, 05:25, mentari <[email protected]> wrote:
> What are your views onhttp://scratchpad.wikia.com/wiki/TileraMulticore
> as a replacement for FPGA's ?
>
> http://www.tilera.com/solutions/digital_baseband.php
>
> The current architecture for base stations fall short of delivering
> the performance, the low latency and the flexibility customers need.
> To meet the requirements, wireless equipment providers design complex
> systems with FPGA, ASIC, DSP and processors with each component
> requiring special tools in a customized development environment. This
> leads to a long development cycle, sometimes years, before
> applications can be productized. Changes in standards also impact
> providers because such systems are inflexible-upgrades can be a slow
> and expensive process.
>
> What providers seek is an uncomplicated, well-designed, architecture
> that yields good performance. Tilera's processors provide a low
> latency single solution that integrates many functions seamlessly in a
> single processor and uses C/C++ to program their applications with
> industry standard tools. The familiar tools enable customers to
> preserve their software investments, replace a number of disparate
> programming methodologies with one standard programming environment,
> and gain the flexibility they need to support evolving protocols and
> ever-increasing demands for service

It seems to be similar to XMOS devices. I suppose that it could
replace FPGAs in some applications. However, it's still a much coarser
architecture than an FPGA. There's still only 64 processing units,
while a Virtex-5 can have about 20 000 slices and a couple of PPC
processors. In the end, I think that since FPGAs are much more
flexible, they have the upper hand. Plus with tools like system
generator, AccelDSP and Simulink, low-level HDL coding can be skipped,
and the engineer can focus more on applications and less on the "bit-
level" of things.

Plus I suppose that with a high-capacity FPGA, one could emulate a
Tilera-like device with 64 processing units. Maybe the future's there,
take the Tilera (or Xmos) concept and implement it in a FPGA.

My 2 cents

On 7 nov, 11:01, Leon <[email protected]> wrote:
> On 7 Nov, 10:25, mentari <[email protected]> wrote:
>
>
>
> > What are your views onhttp://scratchpad.wikia.com/wiki/TileraMulticore
> > as a replacement for FPGA's ?
>
> >http://www.tilera.com/solutions/digital_baseband.php
>
> > The current architecture for base stations fall short of delivering
> > the performance, the low latency and the flexibility customers need.
> > To meet the requirements, wireless equipment providers design complex
> > systems with FPGA, ASIC, DSP and processors with each component
> > requiring special tools in a customized development environment. This
> > leads to a long development cycle, sometimes years, before
> > applications can be productized. Changes in standards also impact
> > providers because such systems are inflexible-upgrades can be a slow
> > and expensive process.
>
> > What providers seek is an uncomplicated, well-designed, architecture
> > that yields good performance. Tilera's processors provide a low
> > latency single solution that integrates many functions seamlessly in a
> > single processor and uses C/C++ to program their applications with
> > industry standard tools. The familiar tools enable customers to
> > preserve their software investments, replace a number of disparate
> > programming methodologies with one standard programming environment,
> > and gain the flexibility they need to support evolving protocols and
> > ever-increasing demands for service
>
> XMOS chips are intended to replace FPGAs in many applications, and are
> available now:
>
> http://www.xmos.com
>
> Leon

So Leon, what's your impression of the xmos devices so far?

On 7 Nov, 16:26, Benjamin Couillard <[email protected]>
wrote:
> On 7 nov, 11:01, Leon <[email protected]> wrote:
>
>
>
> > On 7 Nov, 10:25, mentari <[email protected]> wrote:
>
> > > What are your views onhttp://scratchpad.wikia.com/wiki/TileraMulticore
> > > as a replacement for FPGA's ?
>
> > >http://www.tilera.com/solutions/digital_baseband.php
>
> > > The current architecture for base stations fall short of delivering
> > > the performance, the low latency and the flexibility customers need.
> > > To meet the requirements, wireless equipment providers design complex
> > > systems with FPGA, ASIC, DSP and processors with each component
> > > requiring special tools in a customized development environment. This
> > > leads to a long development cycle, sometimes years, before
> > > applications can be productized. Changes in standards also impact
> > > providers because such systems are inflexible-upgrades can be a slow
> > > and expensive process.
>
> > > What providers seek is an uncomplicated, well-designed, architecture
> > > that yields good performance. Tilera's processors provide a low
> > > latency single solution that integrates many functions seamlessly in a
> > > single processor and uses C/C++ to program their applications with
> > > industry standard tools. The familiar tools enable customers to
> > > preserve their software investments, replace a number of disparate
> > > programming methodologies with one standard programming environment,
> > > and gain the flexibility they need to support evolving protocols and
> > > ever-increasing demands for service
>
> > XMOS chips are intended to replace FPGAs in many applications, and are
> > available now:
>
> >http://www.xmos.com
>
> > Leon
>
> So Leon, what's your impression of the xmos devices so far?

I'm very impressed. The $99 XC-1 kit is very good value, and the
(open source) tools are good. The tools have a few bugs, but they
aren't serious. I don't think the silicon has any problems. Support is
excellent. The chips are made using a conservative 90nm process, when
they move to something more advanced they should be able to push the
speed up and get more cores on a chip; they have said that they
probably won't go over eight cores, though.

Leon

On 7 Nov, 16:11, Benjamin Couillard <[email protected]>
wrote:
> On 7 nov, 05:25, mentari <[email protected]> wrote:
>
>
>
> > What are your views onhttp://scratchpad.wikia.com/wiki/TileraMulticore
> > as a replacement for FPGA's ?
>
> >http://www.tilera.com/solutions/digital_baseband.php
>
> > The current architecture for base stations fall short of delivering
> > the performance, the low latency and the flexibility customers need.
> > To meet the requirements, wireless equipment providers design complex
> > systems with FPGA, ASIC, DSP and processors with each component
> > requiring special tools in a customized development environment. This
> > leads to a long development cycle, sometimes years, before
> > applications can be productized. Changes in standards also impact
> > providers because such systems are inflexible-upgrades can be a slow
> > and expensive process.
>
> > What providers seek is an uncomplicated, well-designed, architecture
> > that yields good performance. Tilera's processors provide a low
> > latency single solution that integrates many functions seamlessly in a
> > single processor and uses C/C++ to program their applications with
> > industry standard tools. The familiar tools enable customers to
> > preserve their software investments, replace a number of disparate
> > programming methodologies with one standard programming environment,
> > and gain the flexibility they need to support evolving protocols and
> > ever-increasing demands for service
>
> It seems to be similar to XMOS devices. I suppose that it could
> replace FPGAs in some applications. However, it's still a much coarser
> architecture than an FPGA. *There's still only 64 processing units,
> while a Virtex-5 can have about 20 000 slices and a couple of PPC
> processors. In the end, I think that since FPGAs are much more
> flexible, they have the upper hand. Plus with tools like system
> generator, AccelDSP and Simulink, low-level HDL coding can be skipped,
> and the engineer can focus more on applications and less on the "bit-
> level" of things.
>
> Plus I suppose that with a high-capacity FPGA, one could emulate a
> Tilera-like device with 64 processing units. Maybe the future's there,
> take the Tilera (or Xmos) concept and implement it in a FPGA.
>
> My 2 cents

They will cost more, be much harder to use, use a lot more power and
won't be any faster.

Leon

On Nov 7, 6:11 pm, Benjamin Couillard <[email protected]>
wrote:
> It seems to be similar to XMOS devices. I suppose that it could
> replace FPGAs in some applications. However, it's still a much coarser
> architecture than an FPGA. There's still only 64 processing units,
> while a Virtex-5 can have about 20 000 slices and a couple of PPC
> processors. In the end, I think that since FPGAs are much more
> flexible, they have the upper hand. Plus with tools like system
> generator, AccelDSP and Simulink, low-level HDL coding can be skipped,
> and the engineer can focus more on applications and less on the "bit-
> level" of things.

How complicated is it to do Viterbi, Reed-Solomon on an FPGA for a
Wimax transmitter on say 2.4ghz implementing OFDM? My understanding is
that that Tilera will provide us with a pure C++ environment and speed
up the development cycle which with FPGA could be a few years for a
full fledged base station.

On 7 nov, 11:47, Leon <[email protected]> wrote:
> On 7 Nov, 16:11, Benjamin Couillard <[email protected]>
> wrote:
>
>
>
> > On 7 nov, 05:25, mentari <[email protected]> wrote:
>
> > > What are your views onhttp://scratchpad.wikia.com/wiki/TileraMulticore
> > > as a replacement for FPGA's ?
>
> > >http://www.tilera.com/solutions/digital_baseband.php
>
> > > The current architecture for base stations fall short of delivering
> > > the performance, the low latency and the flexibility customers need.
> > > To meet the requirements, wireless equipment providers design complex
> > > systems with FPGA, ASIC, DSP and processors with each component
> > > requiring special tools in a customized development environment. This
> > > leads to a long development cycle, sometimes years, before
> > > applications can be productized. Changes in standards also impact
> > > providers because such systems are inflexible-upgrades can be a slow
> > > and expensive process.
>
> > > What providers seek is an uncomplicated, well-designed, architecture
> > > that yields good performance. Tilera's processors provide a low
> > > latency single solution that integrates many functions seamlessly in a
> > > single processor and uses C/C++ to program their applications with
> > > industry standard tools. The familiar tools enable customers to
> > > preserve their software investments, replace a number of disparate
> > > programming methodologies with one standard programming environment,
> > > and gain the flexibility they need to support evolving protocols and
> > > ever-increasing demands for service
>
> > It seems to be similar to XMOS devices. I suppose that it could
> > replace FPGAs in some applications. However, it's still a much coarser
> > architecture than an FPGA. *There's still only 64 processing units,
> > while a Virtex-5 can have about 20 000 slices and a couple of PPC
> > processors. In the end, I think that since FPGAs are much more
> > flexible, they have the upper hand. Plus with tools like system
> > generator, AccelDSP and Simulink, low-level HDL coding can be skipped,
> > and the engineer can focus more on applications and less on the "bit-
> > level" of things.
>
> > Plus I suppose that with a high-capacity FPGA, one could emulate a
> > Tilera-like device with 64 processing units. Maybe the future's there,
> > take the Tilera (or Xmos) concept and implement it in a FPGA.
>
> > My 2 cents
>
> They will cost more, be much harder to use, use a lot more power and
> won't be any faster.
>
> Leon

THe point is not that it will be faster, is that it'll be much more
versatile since you won't be stuck with a fixed architecture

On 7 Nov, 18:00, Benjamin Couillard <[email protected]>
wrote:
> On 7 nov, 11:47, Leon <[email protected]> wrote:
>
>
>
> > On 7 Nov, 16:11, Benjamin Couillard <[email protected]>
> > wrote:
>
> > > On 7 nov, 05:25, mentari <[email protected]> wrote:
>
> > > > What are your views onhttp://scratchpad.wikia.com/wiki/TileraMulticore
> > > > as a replacement for FPGA's ?
>
> > > >http://www.tilera.com/solutions/digital_baseband.php
>
> > > > The current architecture for base stations fall short of delivering
> > > > the performance, the low latency and the flexibility customers need..
> > > > To meet the requirements, wireless equipment providers design complex
> > > > systems with FPGA, ASIC, DSP and processors with each component
> > > > requiring special tools in a customized development environment. This
> > > > leads to a long development cycle, sometimes years, before
> > > > applications can be productized. Changes in standards also impact
> > > > providers because such systems are inflexible-upgrades can be a slow
> > > > and expensive process.
>
> > > > What providers seek is an uncomplicated, well-designed, architecture
> > > > that yields good performance. Tilera's processors provide a low
> > > > latency single solution that integrates many functions seamlessly in a
> > > > single processor and uses C/C++ to program their applications with
> > > > industry standard tools. The familiar tools enable customers to
> > > > preserve their software investments, replace a number of disparate
> > > > programming methodologies with one standard programming environment,
> > > > and gain the flexibility they need to support evolving protocols and
> > > > ever-increasing demands for service
>
> > > It seems to be similar to XMOS devices. I suppose that it could
> > > replace FPGAs in some applications. However, it's still a much coarser
> > > architecture than an FPGA. *There's still only 64 processing units,
> > > while a Virtex-5 can have about 20 000 slices and a couple of PPC
> > > processors. In the end, I think that since FPGAs are much more
> > > flexible, they have the upper hand. Plus with tools like system
> > > generator, AccelDSP and Simulink, low-level HDL coding can be skipped,
> > > and the engineer can focus more on applications and less on the "bit-
> > > level" of things.
>
> > > Plus I suppose that with a high-capacity FPGA, one could emulate a
> > > Tilera-like device with 64 processing units. Maybe the future's there,
> > > take the Tilera (or Xmos) concept and implement it in a FPGA.
>
> > > My 2 cents
>
> > They will cost more, be much harder to use, use a lot more power and
> > won't be any faster.
>
> > Leon
>
> THe point is not that it will be faster, is that it'll be much more
> versatile since you won't be stuck with a fixed architecture

You won't have 64k per core, and what about stuff like 100 MHz I/Os,
hardware threads switching in one cycle, and 3.2 Gb/s full duplex
links between cores?

Leon

On 7 nov, 14:00, Leon <[email protected]> wrote:
> On 7 Nov, 18:00, Benjamin Couillard <[email protected]>
> wrote:
>
>
>
> > On 7 nov, 11:47, Leon <[email protected]> wrote:
>
> > > On 7 Nov, 16:11, Benjamin Couillard <[email protected]>
> > > wrote:
>
> > > > On 7 nov, 05:25, mentari <[email protected]> wrote:
>
> > > > > What are your views onhttp://scratchpad.wikia.com/wiki/TileraMulticore
> > > > > as a replacement for FPGA's ?
>
> > > > >http://www.tilera.com/solutions/digital_baseband.php
>
> > > > > The current architecture for base stations fall short of delivering
> > > > > the performance, the low latency and the flexibility customers need.
> > > > > To meet the requirements, wireless equipment providers design complex
> > > > > systems with FPGA, ASIC, DSP and processors with each component
> > > > > requiring special tools in a customized development environment. This
> > > > > leads to a long development cycle, sometimes years, before
> > > > > applications can be productized. Changes in standards also impact
> > > > > providers because such systems are inflexible-upgrades can be a slow
> > > > > and expensive process.
>
> > > > > What providers seek is an uncomplicated, well-designed, architecture
> > > > > that yields good performance. Tilera's processors provide a low
> > > > > latency single solution that integrates many functions seamlesslyin a
> > > > > single processor and uses C/C++ to program their applications with
> > > > > industry standard tools. The familiar tools enable customers to
> > > > > preserve their software investments, replace a number of disparate
> > > > > programming methodologies with one standard programming environment,
> > > > > and gain the flexibility they need to support evolving protocols and
> > > > > ever-increasing demands for service
>
> > > > It seems to be similar to XMOS devices. I suppose that it could
> > > > replace FPGAs in some applications. However, it's still a much coarser
> > > > architecture than an FPGA. *There's still only 64 processing units,
> > > > while a Virtex-5 can have about 20 000 slices and a couple of PPC
> > > > processors. In the end, I think that since FPGAs are much more
> > > > flexible, they have the upper hand. Plus with tools like system
> > > > generator, AccelDSP and Simulink, low-level HDL coding can be skipped,
> > > > and the engineer can focus more on applications and less on the "bit-
> > > > level" of things.
>
> > > > Plus I suppose that with a high-capacity FPGA, one could emulate a
> > > > Tilera-like device with 64 processing units. Maybe the future's there,
> > > > take the Tilera (or Xmos) concept and implement it in a FPGA.
>
> > > > My 2 cents
>
> > > They will cost more, be much harder to use, use a lot more power and
> > > won't be any faster.
>
> > > Leon
>
> > THe point is not that it will be faster, is that it'll be much more
> > versatile since you won't be stuck with a fixed architecture
>
> You won't have 64k per core, and what about stuff like 100 MHz I/Os,
> hardware threads switching in one cycle, and 3.2 Gb/s full duplex
> links between cores?
>
> Leon

You raise some good points.
But, I was just making the point that you could implement some sort of
"xmos-like" architecture in a big FPGA. While you wouldn't have 64k
per core , you would certainly be able to have 3.2 Gb/s full duplex
(32 bits @ 100 MHz).

But anyay, I think that FPGAs are there to stay and they have a big
future in front of them. There might be some applications where
they'll be replaced by faster, cheaper technologies, but the reverse
is also true.

mentari <[email protected]> writes:

> What are your views on http://scratchpad.wikia.com/wiki/TileraMulticore

Are they cache coherent? If not what types of libraries do they
provide, e.g. is MPI supported? What about debuggers for the
architecture?

Petter
--
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

On 7 Nov, 19:26, Benjamin Couillard <[email protected]>
wrote:
> On 7 nov, 14:00, Leon <[email protected]> wrote:
>
>
>
> > On 7 Nov, 18:00, Benjamin Couillard <[email protected]>
> > wrote:
>
> > > On 7 nov, 11:47, Leon <[email protected]> wrote:
>
> > > > On 7 Nov, 16:11, Benjamin Couillard <[email protected]>
> > > > wrote:
>
> > > > > On 7 nov, 05:25, mentari <[email protected]> wrote:
>
> > > > > > What are your views onhttp://scratchpad.wikia.com/wiki/TileraMulticore
> > > > > > as a replacement for FPGA's ?
>
> > > > > >http://www.tilera.com/solutions/digital_baseband.php
>
> > > > > > The current architecture for base stations fall short of delivering
> > > > > > the performance, the low latency and the flexibility customers need.
> > > > > > To meet the requirements, wireless equipment providers design complex
> > > > > > systems with FPGA, ASIC, DSP and processors with each component
> > > > > > requiring special tools in a customized development environment.. This
> > > > > > leads to a long development cycle, sometimes years, before
> > > > > > applications can be productized. Changes in standards also impact
> > > > > > providers because such systems are inflexible-upgrades can be aslow
> > > > > > and expensive process.
>
> > > > > > What providers seek is an uncomplicated, well-designed, architecture
> > > > > > that yields good performance. Tilera's processors provide a low
> > > > > > latency single solution that integrates many functions seamlessly in a
> > > > > > single processor and uses C/C++ to program their applications with
> > > > > > industry standard tools. The familiar tools enable customers to
> > > > > > preserve their software investments, replace a number of disparate
> > > > > > programming methodologies with one standard programming environment,
> > > > > > and gain the flexibility they need to support evolving protocols and
> > > > > > ever-increasing demands for service
>
> > > > > It seems to be similar to XMOS devices. I suppose that it could
> > > > > replace FPGAs in some applications. However, it's still a much coarser
> > > > > architecture than an FPGA. *There's still only 64 processing units,
> > > > > while a Virtex-5 can have about 20 000 slices and a couple of PPC
> > > > > processors. In the end, I think that since FPGAs are much more
> > > > > flexible, they have the upper hand. Plus with tools like system
> > > > > generator, AccelDSP and Simulink, low-level HDL coding can be skipped,
> > > > > and the engineer can focus more on applications and less on the "bit-
> > > > > level" of things.
>
> > > > > Plus I suppose that with a high-capacity FPGA, one could emulate a
> > > > > Tilera-like device with 64 processing units. Maybe the future's there,
> > > > > take the Tilera (or Xmos) concept and implement it in a FPGA.
>
> > > > > My 2 cents
>
> > > > They will cost more, be much harder to use, use a lot more power and
> > > > won't be any faster.
>
> > > > Leon
>
> > > THe point is not that it will be faster, is that it'll be much more
> > > versatile since you won't be stuck with a fixed architecture
>
> > You won't have 64k per core, and what about stuff like 100 MHz I/Os,
> > hardware threads switching in one cycle, and 3.2 Gb/s full duplex
> > links between cores?
>
> > Leon
>
> You raise some good points.
> But, I was just making the point that you could implement some sort of
> "xmos-like" architecture in a big FPGA. While you wouldn't have 64k
> per core , you would certainly be able to have 3.2 Gb/s full duplex
> (32 bits @ 100 MHz).
>
> But anyay, I think that FPGAs are there to stay and they have a big
> future in front of them. There might be some applications where
> they'll be replaced by faster, cheaper technologies, but the reverse
> is also true.

They won't replace them completely, of course, but there will be many
applications where the ease of development (a C-like language with
compilation and testing in a few seconds) and low cost will see them
being used in place of FPGAs, and in conjunction with them. One
application I've heard of uses a CPLD as an XLink interface to an XMOS
chip, and I'm thinking of using an FPGA between an RF ADC and the XMOS
chip for a software defined radio.

Leon

Benjamin Couillard wrote:
> You raise some good points.
> But, I was just making the point that you could implement some sort of
> "xmos-like" architecture in a big FPGA. While you wouldn't have 64k
> per core , you would certainly be able to have 3.2 Gb/s full duplex
> (32 bits @ 100 MHz).
>
> But anyay, I think that FPGAs are there to stay and they have a big
> future in front of them. There might be some applications where
> they'll be replaced by faster, cheaper technologies, but the reverse
> is also true.


True, but FPGA markets will suffer from short lifetimes. As soon
as the use gets sufficently stable, and the volumes ramp, someone
comes along with a Silicon solution that displaces the FPGA

Here is a good example = Freescale have just released a 6 core DSP
http://www.freescale.com%2F&esheet=5...le.com&index=1

This targets applications that used DSP+FPGA before.

Of course, the MSC8156 AND a FPGA will be more powerful again...

-jg

Mentari -

Please do us the favor of identifying yourself as an interested party
in Tilera or tell us why you're posting here in comp.arch.fpga with
absolutely no apparent history in this newsgroup.

It's often okay for an occasional post from a company with a new,
compelling architecture to stir interest on a very related newsgroup,
but not so much through pretext. Participants in this newsgroup have
had tremendous interactions in the past with professionals from the
compainies involved in products for the markets we work in.

Personally, I don't like people passing themselves off as "random
interested party" when they're a pump & dump investor or a marketing
person trying to "sneak in" some interest as if it's a grass roots
effort.

If you have no affiliation with the company or its products, you are
certainly an unusual participant in this group with complete, well
thought-out communication down to the detail of your diction to the
extent that engineering doesn't appear to your primary interest.
Engineers can communicate well but we're often more interested in the
meat and meaning of the conversation rather than well considered
prose. You look like marketing.

If you really are an interested engineer, more power to ya. But I
don't like looking at threads with strong suspicion.

- John_H

On Nov 7, 11:09 pm, John_H <[email protected]> wrote:
> Mentari -
>
> Please do us the favor of identifying yourself as an interested party
> in Tilera or tell us why you're posting here in comp.arch.fpga with
> absolutely no apparent history in this newsgroup.

I am not a engineer just somebody trying to figure out what it will
cost to pay an FPGA engineer to build a ODFM LTE or Wimax base station
that I can interface to any http://scratchpad.wikia.com/wiki/RfTransceiver

I have contacted http://scratchpad.wikia.com/wiki/SeaSolve but they
don't license their 802.16e MAC and PHY cores to the public only to
Telco's. Is there some sort of conspiracy by Vodacom to prevent
people from building their own Wimax towers on say 450mhz like Flarion
FLASH-OFDM in the Nordic countries. ? How complicated is it our how
long will it take an engineer to build 802.16e MAC/PHY and at what
cost.

Please help me out.

Leon schrieb:
> On 7 Nov, 19:26, Benjamin Couillard <[email protected]>
> wrote:
>> On 7 nov, 14:00, Leon <[email protected]> wrote:
>>
>>
>>
>>> On 7 Nov, 18:00, Benjamin Couillard <[email protected]>
>>> wrote:
>>>> On 7 nov, 11:47, Leon <[email protected]> wrote:
>>>>> On 7 Nov, 16:11, Benjamin Couillard <[email protected]>
>>>>> wrote:
>>>>>> On 7 nov, 05:25, mentari <[email protected]> wrote:
>>>>>>> What are your views onhttp://scratchpad.wikia.com/wiki/TileraMulticore
>>>>>>> as a replacement for FPGA's ?
>>>>>>> http://www.tilera.com/solutions/digital_baseband.php
>>>>>>> The current architecture for base stations fall short of delivering
>>>>>>> the performance, the low latency and the flexibility customers need.
>>>>>>> To meet the requirements, wireless equipment providers design complex
>>>>>>> systems with FPGA, ASIC, DSP and processors with each component
>>>>>>> requiring special tools in a customized development environment. This
>>>>>>> leads to a long development cycle, sometimes years, before
>>>>>>> applications can be productized. Changes in standards also impact
>>>>>>> providers because such systems are inflexible-upgrades can be a slow
>>>>>>> and expensive process.
>>>>>>> What providers seek is an uncomplicated, well-designed, architecture
>>>>>>> that yields good performance. Tilera's processors provide a low
>>>>>>> latency single solution that integrates many functions seamlessly in a
>>>>>>> single processor and uses C/C++ to program their applications with
>>>>>>> industry standard tools. The familiar tools enable customers to
>>>>>>> preserve their software investments, replace a number of disparate
>>>>>>> programming methodologies with one standard programming environment,
>>>>>>> and gain the flexibility they need to support evolving protocols and
>>>>>>> ever-increasing demands for service
>>>>>> It seems to be similar to XMOS devices. I suppose that it could
>>>>>> replace FPGAs in some applications. However, it's still a much coarser
>>>>>> architecture than an FPGA. There's still only 64 processing units,
>>>>>> while a Virtex-5 can have about 20 000 slices and a couple of PPC
>>>>>> processors. In the end, I think that since FPGAs are much more
>>>>>> flexible, they have the upper hand. Plus with tools like system
>>>>>> generator, AccelDSP and Simulink, low-level HDL coding can be skipped,
>>>>>> and the engineer can focus more on applications and less on the "bit-
>>>>>> level" of things.
>>>>>> Plus I suppose that with a high-capacity FPGA, one could emulate a
>>>>>> Tilera-like device with 64 processing units. Maybe the future's there,
>>>>>> take the Tilera (or Xmos) concept and implement it in a FPGA.
>>>>>> My 2 cents
>>>>> They will cost more, be much harder to use, use a lot more power and
>>>>> won't be any faster.
>>>>> Leon
>>>> THe point is not that it will be faster, is that it'll be much more
>>>> versatile since you won't be stuck with a fixed architecture
>>> You won't have 64k per core, and what about stuff like 100 MHz I/Os,
>>> hardware threads switching in one cycle, and 3.2 Gb/s full duplex
>>> links between cores?
>>> Leon
>> You raise some good points.
>> But, I was just making the point that you could implement some sort of
>> "xmos-like" architecture in a big FPGA. While you wouldn't have 64k
>> per core , you would certainly be able to have 3.2 Gb/s full duplex
>> (32 bits @ 100 MHz).
>>
>> But anyay, I think that FPGAs are there to stay and they have a big
>> future in front of them. There might be some applications where
>> they'll be replaced by faster, cheaper technologies, but the reverse
>> is also true.
>
> They won't replace them completely, of course, but there will be many
> applications where the ease of development (a C-like language with
> compilation and testing in a few seconds) and low cost will see them
> being used in place of FPGAs, and in conjunction with them. One
> application I've heard of uses a CPLD as an XLink interface to an XMOS
> chip, and I'm thinking of using an FPGA between an RF ADC and the XMOS
> chip for a software defined radio.
>
> Leon

When I talked to the XMOS guys they told me about the programmable and
highly flexible IOs. That suggested somehow that you should not need an FPGA
to glue the ADC to the XMOS chip. Can you tell us why this cannot be done?

-Markus

On 10 Nov, 07:22, Markus <[email protected]> wrote:
> Leon schrieb:
>
>
>
> > On 7 Nov, 19:26, Benjamin Couillard <[email protected]>
> > wrote:
> >> On 7 nov, 14:00, Leon <[email protected]> wrote:
>
> >>> On 7 Nov, 18:00, Benjamin Couillard <[email protected]>
> >>> wrote:
> >>>> On 7 nov, 11:47, Leon <[email protected]> wrote:
> >>>>> On 7 Nov, 16:11, Benjamin Couillard <[email protected]>
> >>>>> wrote:
> >>>>>> On 7 nov, 05:25, mentari <[email protected]> wrote:
> >>>>>>> What are your views onhttp://scratchpad.wikia.com/wiki/TileraMulticore
> >>>>>>> as a replacement for FPGA's ?
> >>>>>>>http://www.tilera.com/solutions/digital_baseband.php
> >>>>>>> The current architecture for base stations fall short of delivering
> >>>>>>> the performance, the low latency and the flexibility customers need.
> >>>>>>> To meet the requirements, wireless equipment providers design complex
> >>>>>>> systems with FPGA, ASIC, DSP and processors with each component
> >>>>>>> requiring special tools in a customized development environment. This
> >>>>>>> leads to a long development cycle, sometimes years, before
> >>>>>>> applications can be productized. Changes in standards also impact
> >>>>>>> providers because such systems are inflexible-upgrades can be a slow
> >>>>>>> and expensive process.
> >>>>>>> What providers seek is an uncomplicated, well-designed, architecture
> >>>>>>> that yields good performance. Tilera's processors provide a low
> >>>>>>> latency single solution that integrates many functions seamlesslyin a
> >>>>>>> single processor and uses C/C++ to program their applications with
> >>>>>>> industry standard tools. The familiar tools enable customers to
> >>>>>>> preserve their software investments, replace a number of disparate
> >>>>>>> programming methodologies with one standard programming environment,
> >>>>>>> and gain the flexibility they need to support evolving protocols and
> >>>>>>> ever-increasing demands for service
> >>>>>> It seems to be similar to XMOS devices. I suppose that it could
> >>>>>> replace FPGAs in some applications. However, it's still a much coarser
> >>>>>> architecture than an FPGA. *There's still only 64 processing units,
> >>>>>> while a Virtex-5 can have about 20 000 slices and a couple of PPC
> >>>>>> processors. In the end, I think that since FPGAs are much more
> >>>>>> flexible, they have the upper hand. Plus with tools like system
> >>>>>> generator, AccelDSP and Simulink, low-level HDL coding can be skipped,
> >>>>>> and the engineer can focus more on applications and less on the "bit-
> >>>>>> level" of things.
> >>>>>> Plus I suppose that with a high-capacity FPGA, one could emulate a
> >>>>>> Tilera-like device with 64 processing units. Maybe the future's there,
> >>>>>> take the Tilera (or Xmos) concept and implement it in a FPGA.
> >>>>>> My 2 cents
> >>>>> They will cost more, be much harder to use, use a lot more power and
> >>>>> won't be any faster.
> >>>>> Leon
> >>>> THe point is not that it will be faster, is that it'll be much more
> >>>> versatile since you won't be stuck with a fixed architecture
> >>> You won't have 64k per core, and what about stuff like 100 MHz I/Os,
> >>> hardware threads switching in one cycle, and 3.2 Gb/s full duplex
> >>> links between cores?
> >>> Leon
> >> You raise some good points.
> >> But, I was just making the point that you could implement some sort of
> >> "xmos-like" architecture in a big FPGA. While you wouldn't have 64k
> >> per core , you would certainly be able to have 3.2 Gb/s full duplex
> >> (32 bits @ 100 MHz).
>
> >> But anyay, I think that FPGAs are there to stay and they have a big
> >> future in front of them. There might be some applications where
> >> they'll be replaced by faster, cheaper technologies, but the reverse
> >> is also true.
>
> > They won't replace them completely, of course, but there will be many
> > applications where the ease of development (a C-like language with
> > compilation *and testing in a few seconds) and low cost will see them
> > being used in place of FPGAs, and in conjunction with them. One
> > application I've heard of uses a CPLD as an XLink interface to an XMOS
> > chip, and I'm thinking of using an FPGA between an RF ADC and the XMOS
> > chip for a software defined radio.
>
> > Leon
>
> When I talked to the XMOS guys they told me about the programmable and
> highly flexible IOs. That suggested somehow that you should not need an FPGA
> to glue the ADC to the XMOS chip. Can you tell us why this cannot be done?
>
> -Markus

I don't think it's fast enough, I might try it though. I'll only need
a small FPGA.

Leon

>How complicated is it to do Viterbi, Reed-Solomon on an FPGA for a
>Wimax transmitter on say 2.4ghz implementing OFDM? My understanding is
>that that Tilera will provide us with a pure C++ environment and speed
>up the development cycle which with FPGA could be a few years for a
>full fledged base station.

In a typical system, you might have an FPGA do the arithmetic core,
possibly with an auxiliary DSP, and some small linux microprocessor off
the side running control services. The Tilera chip covers all those.

--
mac the naïf