FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > FPGA

FPGA comp.arch.fpga newsgroup (usenet)

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 11-13-2003, 10:53 AM
Holger
Guest
 
Posts: n/a
Default SystemC Implementation

Hi people, can anybody help me?
I want to implement a clock process in a modul to generate a
independent testbench. My gain is to translate the systemc-code to
vhdl and simulate the projekt in vhdl. It is possible to implement
sc_clock outside sc_main(), but i can not use the parameters for
example sc_clock clk("Clk",20 ,0.5,2,true).

Have anybody a similar problem and have you found a solution?

Thanks.
Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
why systemc? [email protected] Verilog 15 12-06-2004 10:41 AM
SystemC Implementation Holger FPGA 0 11-13-2003 10:53 AM


All times are GMT +1. The time now is 11:03 AM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved