FPGA Central

What is the general view on the usefulness/value
of systemc?
I very familiar with Verilog and used to be
very familiar with VHDL.
Systemc seems to be lower level where you
are almost writing the simuator. That would
appear to give more flexibility and abstraction.
But after you've completed the systemc design
it appears you have to rewrite it in a language
that can be synthesized in order to actually
make a chip.
Any comments?

--
rb

On Sun, 16 Apr 2006 00:19:22 GMT, "Ron Baker, Pluralitas!"
<[email protected]> wrote:

>What is the general view on the usefulness/value
>of systemc?
>I very familiar with Verilog and used to be
>very familiar with VHDL.
>Systemc seems to be lower level where you
>are almost writing the simuator. That would
>appear to give more flexibility and abstraction.
>But after you've completed the systemc design
>it appears you have to rewrite it in a language
>that can be synthesized in order to actually
>make a chip.
>Any comments?

I am not sure why you say systemc is lower level. I have the opposite
impression. Also there are systemc synthesizers. It's also quite a bit
faster to simulate. As someone who writes C++ models using a
self-developed fixed-point class library, I welcome systemc.

"mk" <kal*@dspia.*comdelete> wrote in message
news:[email protected]...
> On Sun, 16 Apr 2006 00:19:22 GMT, "Ron Baker, Pluralitas!"
> <[email protected]> wrote:
>
>>What is the general view on the usefulness/value
>>of systemc?
>>I very familiar with Verilog and used to be
>>very familiar with VHDL.
>>Systemc seems to be lower level where you
>>are almost writing the simuator. That would
>>appear to give more flexibility and abstraction.
>>But after you've completed the systemc design
>>it appears you have to rewrite it in a language
>>that can be synthesized in order to actually
>>make a chip.
>>Any comments?
>
> I am not sure why you say systemc is lower level.

You raise an interesting point. Systemc is basically
an extension of c++. C++ is a software language
and not even a high level software language per
the traditional description. (C has been described
as 'portable assembler'.) When one writes in
Systemc much of what one is writing are things that
I recognize as being internal to traditional simulators
such as Modelsim and nc-verilog.
In those senses SystemC is low level.

Being low level like that it is less constrained
and allows more abstract/behavioral coding.
Abstract/behavioral coding can be considered
high level.

> I have the opposite
> impression. Also there are systemc synthesizers.

Interesting. Can you name some?
I asked the prof about that and he gave no
indication that there were such.
I can imagine that there would be synthesizers
for SystemC but I would expect they would
be distinctly limited in the range of possible contructs
that can be synthesized.

> It's also quite a bit
> faster to simulate.

Interesting. In my minimal experience so far
it seems slower to compile but faster
to run. And now that I think about it, run time
is more critical.

> As someone who writes C++ models using a
> self-developed fixed-point class library, I welcome systemc.

Interesting.

Another thought that comes to mind is regarding
graphical debugging tools. With a traditional
HDL and simulator one can probe and graphically display
internal signals. I haven't seen that capability with
SystemC. What I've seen so far is like the earliest
crude HDL simulators that only had text based output.
If you've got a complete, working, self-checking testbench
that's just fine. All it has to do is print 'Pass' or 'Fail'.
But in order to produce a testbench a graphical display
of internal signals is essential.

--
rb

"Ron Baker, Pluralitas!" <[email protected]> wrote in message
news:[email protected]...
>>
>> I am not sure why you say systemc is lower level.
>
> You raise an interesting point. Systemc is basically
> an extension of c++.

It is more than an extension to C++, it includes a cycles based simulator
and VCD dumping support.

> C++ is a software language
> and not even a high level software language per
> the traditional description.

IMHO C++ is a high level language, why do you think it isn't?

> (C has been described
> as 'portable assembler'.) When one writes in
> Systemc much of what one is writing are things that
> I recognize as being internal to traditional simulators
> such as Modelsim and nc-verilog.
> In those senses SystemC is low level.

Check out the appendix in the OSCI SystemC userguide, if you want you can
use HDL style programming for SystemC.

>
> Being low level like that it is less constrained
> and allows more abstract/behavioral coding.
> Abstract/behavioral coding can be considered
> high level.
>
>> I have the opposite
>> impression. Also there are systemc synthesizers.
>
> Interesting. Can you name some?

What about Catapult-C, Agility, Forthe?

> I asked the prof about that and he gave no
> indication that there were such.

And he is a "prof" in.............:-)

> I can imagine that there would be synthesizers
> for SystemC but I would expect they would
> be distinctly limited in the range of possible contructs
> that can be synthesized.

Check out the (not yet ratified) synthesisable SystemC subset.

>
>> It's also quite a bit
>> faster to simulate.
>
> Interesting. In my minimal experience so far
> it seems slower to compile but faster
> to run. And now that I think about it, run time
> is more critical.
>
>> As someone who writes C++ models using a
>> self-developed fixed-point class library, I welcome systemc.
>
> Interesting.
>
> Another thought that comes to mind is regarding
> graphical debugging tools. With a traditional
> HDL and simulator one can probe and graphically display
> internal signals. I haven't seen that capability with
> SystemC.

Check out Modelsim, you get nearly the same capability as the supported HDL
languages, in addition you can display transactors in the next upcoming 6.2
release. I assume NCSim and others will or have the same capability.

> What I've seen so far is like the earliest
> crude HDL simulators that only had text based output.
> If you've got a complete, working, self-checking testbench
> that's just fine. All it has to do is print 'Pass' or 'Fail'.
> But in order to produce a testbench a graphical display
> of internal signals is essential.

Even the free OSCI simulator support VCD dumping, run your simulation, log
the signals then use free GTKView or Dinotrace to display them.

SystemC is not perfect (check out the error messages, what a pain!) but
unless Accellera start making noises about SystemVHDL/HypherVHDL or whatever
they call it SystemC is very suitable for testbenches and high level
modeling. Mixing HDL and SystemC is very easy (at least in Modelsim) and
will give you goodies like constraint random/transaction level modelling and
a dead easy C interface :-)

Hans
www.ht-lab.com


>
> --
> rb

"Hans" <[email protected]> wrote in message
news:[email protected]...
> "Ron Baker, Pluralitas!" <[email protected]> wrote in message
> news:[email protected]...
>>>
>>> I am not sure why you say systemc is lower level.
>>
>> You raise an interesting point. Systemc is basically
>> an extension of c++.
>
> It is more than an extension to C++, it includes a cycles based simulator
> and VCD dumping support.
>
>> C++ is a software language
>> and not even a high level software language per
>> the traditional description.
>
> IMHO C++ is a high level language, why do you think it isn't?

First considering C:

http://www.advogato.org/article/759.html
"Is C a "high-level" language? Most would say not"

http://en.wikipedia.org/wiki/High-level_language
"Many programmers today might refer to C as low-level,
as it still allows memory to be accessed by address,
and provides direct access to the assembly level."

http://en.wikipedia.org/wiki/C_programming_language
"C is sometimes referred to (and not always pejoratively)
as "high-level assembly" or "portable assembly". It is
also sometimes referred to as a mid-level language."

And it could be argued that C++ is high level.
It's kinda moot.

>
>> (C has been described
>> as 'portable assembler'.) When one writes in
>> Systemc much of what one is writing are things that
>> I recognize as being internal to traditional simulators
>> such as Modelsim and nc-verilog.
>> In those senses SystemC is low level.
>
> Check out the appendix in the OSCI SystemC userguide, if you want you can
> use HDL style programming for SystemC.
>
>>
>> Being low level like that it is less constrained
>> and allows more abstract/behavioral coding.
>> Abstract/behavioral coding can be considered
>> high level.
>>
>>> I have the opposite
>>> impression. Also there are systemc synthesizers.
>>
>> Interesting. Can you name some?
>
> What about Catapult-C, Agility, Forthe?

Cool. Thanks.

>
>> I asked the prof about that and he gave no
>> indication that there were such.
>
> And he is a "prof" in.............:-)
>
>> I can imagine that there would be synthesizers
>> for SystemC but I would expect they would
>> be distinctly limited in the range of possible contructs
>> that can be synthesized.
>
> Check out the (not yet ratified) synthesisable SystemC subset.

I've done some more googling and have
found some things on that.

>
>>
>>> It's also quite a bit
>>> faster to simulate.
>>
>> Interesting. In my minimal experience so far
>> it seems slower to compile but faster
>> to run. And now that I think about it, run time
>> is more critical.
>>
>>> As someone who writes C++ models using a
>>> self-developed fixed-point class library, I welcome systemc.
>>
>> Interesting.
>>
>> Another thought that comes to mind is regarding
>> graphical debugging tools. With a traditional
>> HDL and simulator one can probe and graphically display
>> internal signals. I haven't seen that capability with
>> SystemC.
>
> Check out Modelsim, you get nearly the same capability as the supported
> HDL languages, in addition you can display transactors in the next
> upcoming 6.2 release. I assume NCSim and others will or have the same
> capability.

Interesting. Sure, that makes sense.
The versions of Modelsim I have access to don't
support SystemC but it only makes sense that newer
versions would.
Then that makes me wonder if you loose the simulation
speed advantage of SystemC when you use it with
a graphical simulator.

(But maybe I'm wrong about SystemC being faster.
http://en.wikipedia.org/wiki/SystemC says:
"The performance of this simulation kernel is not
to be compared with that of commercial
VHDL/Verilog simulators at the present.")

>
>> What I've seen so far is like the earliest
>> crude HDL simulators that only had text based output.
>> If you've got a complete, working, self-checking testbench
>> that's just fine. All it has to do is print 'Pass' or 'Fail'.
>> But in order to produce a testbench a graphical display
>> of internal signals is essential.
>
> Even the free OSCI simulator support VCD dumping, run your simulation, log
> the signals then use free GTKView or Dinotrace to display them.

Interesting. Yes, I will look into the VCD.

>
> SystemC is not perfect (check out the error messages, what a pain!) but
> unless Accellera start making noises about SystemVHDL/HypherVHDL or
> whatever they call it SystemC is very suitable for testbenches and high
> level modeling. Mixing HDL and SystemC is very easy (at least in Modelsim)
> and will give you goodies like constraint random/transaction level
> modelling and a dead easy C interface :-)
>
> Hans
> www.ht-lab.com

Cool. Thanks for your comments.

I checked out your web page too.
Pretty good.

--
rb