FPGA Central

Hi,

For one of my applications,I was coding in Behavioral Level(vhdl) for
a non-pipelined matrix multiplication(only combinational logic).The
functional simulation went fine.Though synthesis went on without any
erros, XST did not extract any multipliers/adders(I did enable the
options in synthesis properties).XST documentation says it can
synthesize upto 3 dimensional arrays.

I don't want to write a structural vhdl in terms of multipliers and
adders.
Should I unroll the loops!!
Suggestions concerning my coding style,modification etc will be very
helpful.

regards
--raj


----------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity matrix_multiply is
port (
init : in std_logic;
select_in: in std_logic_vector(3 downto 0);
done : out std_logic_vector(15 downto 0)
);

end matrix_multiply;

architecture Behavioral of matrix_multiply is
---------------------------------------------
subtype WORD8 is integer range 0 to 255;
type TAB4 is array (3 downto 0) of WORD8; --one dimension of matrix
type TAB4x4 is array (3 downto 0) of TAB4;
signal MATRIXA,MATRIXB :TAB4X4;

----------------------------------------------------
subtype WORDBIT is std_logic_vector(15 downto 0);
type OUT4 is array (3 downto 0) of WORDBIT;-- one dimension of
matrix
type OUT4x4 is array (3 downto 0) of OUT4;
signal MATRIXC:OUT4X4;


--------------------------------------------

--------------------------------------------

constant CST_A : TAB4x4 := (
(5,6,7,8),
(1,2,3,4),
(2,4,5,8),
(1,1,1,1)

);


constant CST_B : TAB4x4 := (
(2,3,4,5),
(1,2,3,4),
(6,7,6,8),
(1,1,1,1)

);
constant CST_C : OUT4x4 := (
((others=>'0'),(others=>'0'),(others=>'0'),(others =>'0')),
((others=>'0'),(others=>'0'),(others=>'0'),(others =>'0')),
((others=>'0'),(others=>'0'),(others=>'0'),(others =>'0')),
((others=>'0'),(others=>'0'),(others=>'0'),(others =>'0'))

);



begin

MATRIXA<=CST_A;
MATRIXB<=CST_B;
---------------CORE----------------
process(init,MATRIXC)
variable temp:integer;
begin
if(init='0')then
MATRIXC<=CST_C;
else
for row in 0 to 3 loop
for col in 0 to 3 loop
temp:=0;
for k in 0 to 3 loop
temp:=temp+(MATRIXA(row)(k)* MATRIXB(k)(col));
end loop;
MATRIXC(row)(col)<= CONV_STD_LOGIC_VECTOR(temp,16) ;
end loop;
end loop;
end if;

end process ;
----------SENDING THE OUTPUT--------------------------
done <= MATRIXC(0)(0) when select_in = "0000" else
MATRIXC(0)(1) when select_in = "0001" else
MATRIXC(0)(2) when select_in = "0010" else
MATRIXC(0)(3) when select_in = "0011" else
MATRIXC(1)(0) when select_in = "0100" else
MATRIXC(1)(1) when select_in = "0101" else
MATRIXC(1)(2) when select_in = "0110" else
MATRIXC(1)(3) when select_in = "0111" else
MATRIXC(2)(0) when select_in = "1000" else
MATRIXC(2)(1) when select_in = "1001" else
MATRIXC(2)(2) when select_in = "1010" else
MATRIXC(2)(3) when select_in = "1011" else
MATRIXC(3)(0) when select_in = "1100" else
MATRIXC(3)(1) when select_in = "1101" else
MATRIXC(3)(2) when select_in = "1110" else
MATRIXC(3)(3) when select_in = "1111" else
-----------------------------------------------------