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Old 05-26-2006, 12:33 AM
Roland
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Default Synthesizing VHDL delays [noob]

Hi!

I have a question regarding the VHDL's "after" keyword. I've read that
it is not synthesizable but only used for simulation and I was wondering
if this is true for real-world programs. I'm working with Xilinx
Spartan-2 (so it's Xilinx's systhesizer in question) and I've connected
a soft processor to an external memory chip via my VHDL memory
controller but the design isn't working if I deselect CS at the end of a
cycle. I attempted to create delays using afters, ie. "CS <= '0' after
12ns;", but that doesn't seem to be working. I could be I misinterpreted
the memory's datasheet but these afters are bugging me.

So, will a statement like "CS <= '0' after 12ns;" cause 12ns delay in
the FPGA circutry or not? And if not, how could I create a delay?

Thanx!

- R.
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Old 05-26-2006, 12:38 AM
Antti
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Default Re: Synthesizing VHDL delays [noob]

after is only simulation
you must use some clocked process from some clock to generate the
required timing
antti

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Old 05-26-2006, 12:43 AM
Roland
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Default Re: Synthesizing VHDL delays [noob]

Antti wrote:
> after is only simulation
> you must use some clocked process from some clock to generate the
> required timing


Thanx, I'll try that!

- R.
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