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Old 11-02-2007, 03:46 PM
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Default Synthesizing with specific primitive-elements

Hello,

I want to synthesize my VHDL code targeting an ASIC design, and I want
to do this using as primitive elements only NAND gates and d-flip-
flops.

So, basically what I think I have to do is either build a new library
for the synthesizer containing only what I want to use, or use an
existing library excluding all the "building-blocks" I don't want. I
should make clear that I am only interested in getting an RTL
schematic of my synthesized-design, and not getting any back-
annotation information.

Does anyone have any suggestions on how to do this?

I am using Mentor Graphics tools (Leonardo, Precision) but if someone
can suggest a solution even with Cadence tools (or even the rtl-
schematic viewer of xilinx-ISE) it would be greatly appreciated.

Thanks in advance

George (mail: giorgos.puiklis aat gmail.com )

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Old 11-02-2007, 04:09 PM
mk
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Default Re: Synthesizing with specific primitive-elements

On Fri, 02 Nov 2007 14:46:43 -0000, [email protected] wrote:

>Hello,
>
>I want to synthesize my VHDL code targeting an ASIC design, and I want
>to do this using as primitive elements only NAND gates and d-flip-
>flops.
>
>So, basically what I think I have to do is either build a new library
>for the synthesizer containing only what I want to use, or use an
>existing library excluding all the "building-blocks" I don't want. I
>should make clear that I am only interested in getting an RTL
>schematic of my synthesized-design, and not getting any back-
>annotation information.
>
>Does anyone have any suggestions on how to do this?
>
>I am using Mentor Graphics tools (Leonardo, Precision) but if someone
>can suggest a solution even with Cadence tools (or even the rtl-
>schematic viewer of xilinx-ISE) it would be greatly appreciated.
>
>Thanks in advance
>
>George (mail: giorgos.puiklis aat gmail.com )


Almost all synthesis tools have commands like set_dont_utilize or
set_dont_use. You can set all the cells you don't want to don't use
and do your synthesis. But I think you will find it difficult to
convince most synthesizer without an inverter. They don't like making
their inverters from nands so you need to add inverters and change
them back to nands manually/scriptually (?) later.
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Old 11-02-2007, 04:28 PM
John_H
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Default Re: Synthesizing with specific primitive-elements

<[email protected]> wrote in message
news:[email protected] ups.com...
> Hello,
>
> I want to synthesize my VHDL code targeting an ASIC design, and I want
> to do this using as primitive elements only NAND gates and d-flip-
> flops.
>
> So, basically what I think I have to do is either build a new library
> for the synthesizer containing only what I want to use, or use an
> existing library excluding all the "building-blocks" I don't want. I
> should make clear that I am only interested in getting an RTL
> schematic of my synthesized-design, and not getting any back-
> annotation information.
>
> Does anyone have any suggestions on how to do this?
>
> I am using Mentor Graphics tools (Leonardo, Precision) but if someone
> can suggest a solution even with Cadence tools (or even the rtl-
> schematic viewer of xilinx-ISE) it would be greatly appreciated.
>
> Thanks in advance
>
> George (mail: giorgos.puiklis aat gmail.com )


If you're targeting an ASIC, use the ASIC synthesis tools. You'll get
different synthesis results for the same code from XST, Quartus, Synplify,
Synopsys, Mentor, Cadence.... I don't believe the results you get from an
FPGA tool will give you a strong correspondence to your ASIC synthesis
results.

Good luck with your efforts,
- John_H


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  #4 (permalink)  
Old 11-02-2007, 07:12 PM
comp.arch.fpga
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Posts: n/a
Default Re: Synthesizing with specific primitive-elements

On 2 Nov., 15:46, [email protected] wrote:
> Hello,
>
> I want to synthesize my VHDL code targeting an ASIC design, and I want
> to do this using as primitive elements only NAND gates and d-flip-
> flops.
>
> So, basically what I think I have to do is either build a new library
> for the synthesizer containing only what I want to use, or use an
> existing library excluding all the "building-blocks" I don't want. I
> should make clear that I am only interested in getting an RTL
> schematic of my synthesized-design, and not getting any back-
> annotation information.


You are contradicting yourself. The RTL level description usually is
technology independant.
Mapping to your nand only library will be performed in a later step
called "techology mapping".
(First there are likely to be a few other technology indpendant
optimization.)
The result will be a gate level netlist.

Many technolgy mappers start with a representation that only consists
of nand gates, inverters and DFFs.
If you find a way of telling your tool to output that netlist you are
done.

Or use SIS:
http://www1.cs.columbia.edu/~cs4861/s07-sis/sis.1.html

Kolja Sulimma

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