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  #1 (permalink)  
Old 04-27-2006, 03:41 PM
vssumesh
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Default Synplify is not translating xilinx template for block ram

The xilinx template for V4 block ram with one read/write and one
read port is not synthesizing correctly in the synplify. The original
code maps into LUT rams. If we latch the input address and include a
synthesize directive for block RAM then it creates two block RAM
instead of 1 one for each read port. Why it is like that. Is there any
way we can corrct this behaviour.
Else how can we integrate a synthesized output from xilinx to
synplify. That is i want to synthesize the module contaiig this RAM in
xst correctly and then combine that synthesized output to synplify and
then resynthesize it. Is this type of design flow possible.
regards
Sumesh V S

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  #2 (permalink)  
Old 04-27-2006, 06:54 PM
Andy
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Default Re: Synplify is not translating xilinx template for block ram

I've been able to infer dual port block rams in synplify with no
problems before. Can you post a test case that fails? Help us help
you.

Andy

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  #3 (permalink)  
Old 04-27-2006, 11:05 PM
Mike Treseler
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Default Re: Synplify is not translating xilinx template for block ram

vssumesh wrote:
> The xilinx template for V4 block ram with one read/write and one
> read port is not synthesizing correctly in the synplify.


I would start with the synplify template.

-- Mike Treseler
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  #4 (permalink)  
Old 04-28-2006, 03:07 AM
vssumesh
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Default Re: Synplify is not translating xilinx template for block ram

The code which i used from the xilinx template is
always @(posedge clk)
begin
if(we) RAM[addr1] <= in;
out1 <= RAM[addr1];out2 <= RAM[addr2];
end
This created a single block RAM with two out location and a single writ
location.
But if this is used with synpify with /* synthesis syn_ramstyle =
"block_ram" */ directive will give distributed RAM.
Then i tried synplify version

reg [31:0] RAM [15:0] /* synthesis syn_ramstyle = "block_ram" */;
always @(posedge clk)
begin
if(we) RAM[addr1] <= in;
addr1_latch <= addr1; addr2_latch <= addr2;
end
out1 <= RAM[addr1_latch];out2 <= RAM[addr2_latch];

The above code created two block RAM for each output. It is using two
port RAMs but in each RAM second port is unused.

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  #5 (permalink)  
Old 04-28-2006, 06:10 AM
John_H
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Default Re: Synplify is not translating xilinx template for block ram

vssumesh wrote:
> The code which i used from the xilinx template is
> always @(posedge clk)
> begin
> if(we) RAM[addr1] <= in;
> out1 <= RAM[addr1];out2 <= RAM[addr2];
> end
> This created a single block RAM with two out location and a single writ
> location.
> But if this is used with synpify with /* synthesis syn_ramstyle =
> "block_ram" */ directive will give distributed RAM.
> Then i tried synplify version
>
> reg [31:0] RAM [15:0] /* synthesis syn_ramstyle = "block_ram" */;
> always @(posedge clk)
> begin
> if(we) RAM[addr1] <= in;
> addr1_latch <= addr1; addr2_latch <= addr2;
> end
> out1 <= RAM[addr1_latch];out2 <= RAM[addr2_latch];
>
> The above code created two block RAM for each output. It is using two
> port RAMs but in each RAM second port is unused.


It may seem the same, but try

// (using your own dimensions)
wire [n:0] RAM_addr1 /* synthesis syn_keep = 1*/ = RAM[addr1];
wire [n:0] RAM_addr2 /* synthesis syn_keep = 1*/ = RAM[addr2];
always @(posedge clk)
begin
if(we) RAM[addr1] <= in;
out1 <= RAM_addr1;
out2 <= RAM_addr2;
end
______________________

The template I recall includes the write as you show but references by
wires - the syn_keep may not be needed at all but there may be other
aspects of your code that trip up the system.

If your address range is small, try arbitrarily making it BlockRAM sized.

I'll glance at it again when I'm in front of my synthesizer.
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  #6 (permalink)  
Old 04-28-2006, 05:15 PM
vssumesh
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Default Re: Synplify is not translating xilinx template for block ram

Hello John,
This is also not working. It is creating distributed RAMs. Is there
any problem with the version of synplify. I am using 8.0. Also used
syn_ramstyle directive.

One more thing not related to this issue; can you guide me to some good
study materials about synplify synthesize techniques and constrains
(different clock domains, clock relations etc etc). And xilinx PAR
techniques.

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