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  #1 (permalink)  
Old 05-11-2006, 12:08 PM
srini
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Default Synplify - Not satisfactory results with re-timing option

Hi,
I had a strange experience with the Synplify Pro 8.4. I used the
re-timing option thinking that it will help to improve the timing
performance of the design as they have claimed in their docs. But my
design's timing performance has gone down by about 5 Mz and I ended up
not meeting my timing constraints. Why is it so? Can anyone tell me
about this?

Thanks & Regards,
Srini.

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  #2 (permalink)  
Old 05-11-2006, 02:16 PM
Amal
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Default Re: Synplify - Not satisfactory results with re-timing option

I got good results with 8.4, but 8.5 produced a terrible result. But
8.5.1 produces the best of the other two versions. Give it a try if
you can.

-- Amal

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  #3 (permalink)  
Old 05-11-2006, 03:57 PM
Hans
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Default Re: Synplify - Not satisfactory results with re-timing option

Perhaps because retiming in Synplify is using a wireload model? Retiming
works best when you have accurate delay models, i.e. after P&R (even
placement info seems to do the trick). Have a look at Physical synthesis
tools,

Hans.
www.ht-lab.com

"srini" <[email protected]> wrote in message
news:[email protected] oups.com...
> Hi,
> I had a strange experience with the Synplify Pro 8.4. I used the
> re-timing option thinking that it will help to improve the timing
> performance of the design as they have claimed in their docs. But my
> design's timing performance has gone down by about 5 Mz and I ended up
> not meeting my timing constraints. Why is it so? Can anyone tell me
> about this?
>
> Thanks & Regards,
> Srini.
>



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  #4 (permalink)  
Old 05-12-2006, 04:24 AM
Phil Hays
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Default Re: Synplify - Not satisfactory results with re-timing option

"srini" <[email protected]> wrote:

>I had a strange experience with the Synplify Pro 8.4. I used the
>re-timing option thinking that it will help to improve the timing
>performance of the design as they have claimed in their docs. But my
>design's timing performance has gone down by about 5 Mz and I ended up
>not meeting my timing constraints. Why is it so? Can anyone tell me
>about this?


Retiming works very well for some designs, and makes them run faster.
Other designs retiming doesn't work with, for at least three reasons:


1) The resulting design may be larger, with more routing congestion,
and thereby slower. This is most common and most noticeable when the
part is fairly full. The timing failure may not be in the retimed
paths, but may be elsewhere in the design. The best way to make a
full design faster may be to make it smaller. A floorplan might help
as well.


2) The resulting design may not pack as well. This is fairly hard to
both diagnose and to visualize. It is somewhat like the first case,
but from the inside out. If the retiming increases the routing delay
by making the resulting design larger by more than it saves by making
all paths have similar logic delays, then retiming will make the
design slower. The timing failure may not be in the retimed paths,
but may be elsewhere in the design. Again, making the design smaller
may make it faster, and retiming does the reverse.


3) The retiming is done based on estimated routing delay. As an
example, suppose the design had:

FF -> lut -> lut -> FF --------------------------> FF
1 2 3

If the first two FFs can be close together on one corner of the part,
and the last FF must be on the far corner of the part, then retiming
that to:

FF -> lut -> FF -> lut --------------------------> FF
1 2 3

will almost surely make it slower, as the critical path in the first
case was between FF2 and FF3 because of physical placement, and adding
the lut delay just makes it slower.

The synthesis tool estimates based on "wireload models", and the
estimated delays might look like this:

FF -------------> lut -----> lut -----> FF ------> FF
1 2 3

As the synthesis tool has no knowledge where on the die these items
are placed. The weakness of "wireload models" is a large part of the
reason why "physical synthesis" can be useful, as someone has already
commented, as a estimate of routing delays based on a realistic
placement helps the synthesis, even if the placement isn't saved and
reused.


Retiming is a tool, and works well on many problems. Other problems
require different tools.


--
Phil Hays

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  #5 (permalink)  
Old 05-12-2006, 08:58 AM
srini
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Default Re: Synplify - Not satisfactory results with re-timing option

Hi,
Thanks for the detailed explanation Phil.
Can you tell me how to do Physical synthesis and bring in the routing
delays for synthesis. I am using Xilinx ISE 7.1 for PAR. Can physical
synthesis be done with it. How to bring in the routing delays from
Xilinx PAR and use it for synthesis in Synplify Pro?

Thanks & Regards,
Srini.

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  #6 (permalink)  
Old 05-13-2006, 02:29 PM
Phil Hays
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Default Re: Synplify - Not satisfactory results with re-timing option

"srini" <[email protected]> wrote:

>Can you tell me how to do Physical synthesis and bring in the routing
>delays for synthesis. I am using Xilinx ISE 7.1 for PAR. Can physical
>synthesis be done with it. How to bring in the routing delays from
>Xilinx PAR and use it for synthesis in Synplify Pro?


You may be able to vastly improve results by adding syn_keep or
syn_preserve or -routing to key signals, to prevent retiming where it
isn't helping. Or by doing some manual retiming, and turning off the
automatic retiming. Or floorplanning, often placing just a few items
is all that is needed. Start with block rams, multipliers, or
registers at the ends of the failing path(s). Or updating ISE to 8.1
and try "map -timing". Try several things, see what works and doesn't
for your design. I'd suggest trying these before spending more money
on a tool.

Otherwise, talk to Synplicity about "Synplify Premier". Also, there
are other tools by Mentor (and others?), and I have no recent
experience to allow me to give good suggestions as to which to look
at. However, the same warning applies: Not all problems can be
solved by any tool. You probably want to see if you can get an
evaluation version first.


--
Phil Hays

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