FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > FPGA

FPGA comp.arch.fpga newsgroup (usenet)

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 11-16-2004, 09:20 PM
T Lee
Guest
 
Posts: n/a
Default Suggestion for Xilinx parallel port cable replacement.

How about creating a ethernet to jtag cable replacement?

In that case, you only need to write a user mode program to
tunnel (forward) info from network <-> JTAG.

It will make the xmd, xst, etc on both windows and Unix
platform much easier to develop, maintain and use.

TCP/UDP Socket programming is so much easier to develop nad
debug for all the platform.

Right now, I have to build xilinx_pp drivers for different
version of linux kernels.

Does anyone have a patch for xilinx_pp driver for 2.6 kernel
(Redhat FC 3 release)?


-Tony
Reply With Quote
  #2 (permalink)  
Old 11-16-2004, 10:26 PM
Amontec, Larry
Guest
 
Posts: n/a
Default Re: Suggestion for Xilinx parallel port cable replacement.

T Lee wrote:
> How about creating a ethernet to jtag cable replacement?
>
> In that case, you only need to write a user mode program to
> tunnel (forward) info from network <-> JTAG.
>
> It will make the xmd, xst, etc on both windows and Unix
> platform much easier to develop, maintain and use.
>
> TCP/UDP Socket programming is so much easier to develop nad
> debug for all the platform.
>
> Right now, I have to build xilinx_pp drivers for different
> version of linux kernels.
>
> Does anyone have a patch for xilinx_pp driver for 2.6 kernel
> (Redhat FC 3 release)?
>
>
> -Tony


Or use Chameleon POD on www.amontec.com
Reply With Quote
  #3 (permalink)  
Old 11-16-2004, 11:06 PM
Petter Gustad
Guest
 
Posts: n/a
Default Re: Suggestion for Xilinx parallel port cable replacement.

[email protected] (T Lee) writes:

> How about creating a ethernet to jtag cable replacement?


I've made my own Ethernet based programmer. Works on virtually any OS
and does not require a device driver. Also works with Xilinx Impact
and Altera Quartus.

Petter
--
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?
Reply With Quote
  #4 (permalink)  
Old 11-17-2004, 11:55 AM
Laurent Gauch
Guest
 
Posts: n/a
Default Re: Suggestion for Xilinx parallel port cable replacement.

Petter Gustad wrote:
> [email protected] (T Lee) writes:
>
>
>>How about creating a ethernet to jtag cable replacement?

>
>
> I've made my own Ethernet based programmer. Works on virtually any OS
> and does not require a device driver. Also works with Xilinx Impact
> and Altera Quartus.
>
> Petter


Hi Petter,

Could you please tell me how works the interface with Impact and Quartus?

Are there any application notes explaining the how-to-do ?
Reply With Quote
  #5 (permalink)  
Old 11-17-2004, 09:58 PM
T Lee
Guest
 
Posts: n/a
Default Re: Suggestion for Xilinx parallel port cable replacement.

Laurent Gauch <[email protected]> wrote in message news:<[email protected]>.. .
> Petter Gustad wrote:
> > [email protected] (T Lee) writes:
> >
> >
> >>How about creating a ethernet to jtag cable replacement?

> >
> >
> > I've made my own Ethernet based programmer. Works on virtually any OS
> > and does not require a device driver. Also works with Xilinx Impact
> > and Altera Quartus.
> >
> > Petter

>
> Hi Petter,
>
> Could you please tell me how works the interface with Impact and Quartus?
>
> Are there any application notes explaining the how-to-do ?


Yes, Petter, I would love to know how to do this too.

BTW, does it work with xmd?

-Tony
Reply With Quote
  #6 (permalink)  
Old 11-17-2004, 10:04 PM
T Lee
Guest
 
Posts: n/a
Default Re: Suggestion for Xilinx parallel port cable replacement.

"Amontec, Larry" <[email protected]> wrote in message news:<[email protected]>...
> T Lee wrote:
> > How about creating a ethernet to jtag cable replacement?
> >
> > In that case, you only need to write a user mode program to
> > tunnel (forward) info from network <-> JTAG.
> >
> > It will make the xmd, xst, etc on both windows and Unix
> > platform much easier to develop, maintain and use.
> >
> > TCP/UDP Socket programming is so much easier to develop nad
> > debug for all the platform.
> >
> > Right now, I have to build xilinx_pp drivers for different
> > version of linux kernels.
> >
> > Does anyone have a patch for xilinx_pp driver for 2.6 kernel
> > (Redhat FC 3 release)?
> >
> >
> > -Tony

>
> Or use Chameleon POD on www.amontec.com



I check the website. I only find the replacment for parallel port cable.

The HW for ethernet cable is not hard. The more difficult part to get
the software (xmd, impact) working with the new cable.

-Tony
Reply With Quote
  #7 (permalink)  
Old 11-18-2004, 11:35 PM
Petter Gustad
Guest
 
Posts: n/a
Default Re: Suggestion for Xilinx parallel port cable replacement.

Laurent Gauch <[email protected]> writes:

> Could you please tell me how works the interface with Impact and
> Quartus?


Through SVF.

Petter

--
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?
Reply With Quote
  #8 (permalink)  
Old 11-19-2004, 02:08 AM
Gregory C. Read
Guest
 
Posts: n/a
Default Re: Suggestion for Xilinx parallel port cable replacement.

A: Jeopardy.
Q: What is my favorite quiz show?

--
Greg
[email protected]d
(Remove the '.invalid' twice to send Email)

- --
> A: Because it messes up the order in which people normally read text.
> Q: Why is top-posting such a bad thing?
> A: Top-posting.
> Q: What is the most annoying thing on usenet and in e-mail?



Reply With Quote
  #9 (permalink)  
Old 11-19-2004, 09:45 AM
Uwe Bonnes
Guest
 
Posts: n/a
Default Re: Suggestion for Xilinx parallel port cable replacement.

Petter Gustad <[email protected]> wrote:
: [email protected] (T Lee) writes:

: > How about creating a ethernet to jtag cable replacement?

: I've made my own Ethernet based programmer. Works on virtually any OS
: and does not require a device driver. Also works with Xilinx Impact
: and Altera Quartus.

Any chance to see the design or maybe buy units?

--
Uwe Bonnes [email protected]

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
Reply With Quote
  #10 (permalink)  
Old 11-22-2004, 12:08 AM
Petter Gustad
Guest
 
Posts: n/a
Default Re: Suggestion for Xilinx parallel port cable replacement.

Uwe Bonnes <[email protected]> writes:

> Petter Gustad <[email protected]> wrote:
> : [email protected] (T Lee) writes:
>
> : > How about creating a ethernet to jtag cable replacement?
>
> : I've made my own Ethernet based programmer. Works on virtually any OS
> : and does not require a device driver. Also works with Xilinx Impact
> : and Altera Quartus.
>
> Any chance to see the design or maybe buy units?


Unfortunately not yet. I'm currently making this programmer and system
into a product. I'm doing this on my spare time so I move slower than
anticipated, but I'm interested in getting in touch with beta testers
and other interested parties. My e-mail address can be found at
http://www.gustad.com/pics/email.gif

Petter
--
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?
Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
Xilinx JTAG Parallel IV cable and INITIALIZING CHAIN Ronald Chung FPGA 6 02-14-2010 05:30 PM
length of parallel cable attached to P IV xilinx jtag cable Matthew E Rosenthal FPGA 1 06-16-2004 03:01 AM
Xilinx Parallel cable Sumit Gupta FPGA 3 01-05-2004 05:11 PM


All times are GMT +1. The time now is 06:21 PM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved