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Old 01-08-2004, 10:11 AM
Paul
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Default submodules with their own constraint files

Hi

Someone has posted this question earlier but received no response.
But I will try again. Because I think this is an important issue.
People must have either solved this problem by other means.
Or they just enjoy copy and paste the IO pins again and again--as they
get included in the upper modules.

Some IO pins in the submodules can be considered "final" in a design,
since they connect directly to outside the chip.
Why rewirte them again and again and risk the chance of typos.

Why not in the language or in the tools declared them as "final", so
that when they get included in any module -- no matter how many times,
they have their own constaints. This would save a lot of copy and
paste and typos.

Is there any reasons that this shouldn't be done?

Do some people actually enjoy aggregating the IO pins again and again?
Instead of focusing on the design.
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Old 01-09-2004, 06:30 PM
Mike Treseler
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Default Re: submodules with their own constraint files

Paul wrote:

> Some IO pins in the submodules can be considered "final" in a design,
> since they connect directly to outside the chip.
> Why rewirte them again and again and risk the chance of typos.


In VHDL lingo, you are talking about the port maps
within the top entity. Some of these are direct
port to port wires, while others require intermediate
signals.

> Why not in the language or in the tools declared them as "final", so
> that when they get included in any module -- no matter how many times,
> they have their own constaints. This would save a lot of copy and
> paste and typos.


I prefer to maintain constraints in the place and route
files rather than in the source code. For
synchronous designs, you don't need very many.

> Do some people actually enjoy aggregating the IO pins again and again?
> Instead of focusing on the design.


I expect that most people don't.
I let emacs vhdl-mode port cut/paste do this for me.

-- Mike Treseler

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