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  #1 (permalink)  
Old 11-12-2007, 03:55 PM
Sascha Frank
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Default Strange VHDL Error

Hi

I have a simple package that looks as follows:

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;


package RISC_Pkg is

-- Clock type
subtype T_clk is std_logic;

-- Reset type
subtype T_rst is std_logic;

subtype T_PIPE_REG_CTRL is std_logic;

subtype T_PREG_FE_DC_dest_pi is unsigned(7 downto 0);
subtype T_FLAG_PREG_FE_DC_dest_pi is std_logic;
subtype T_DATABUS_FE_DC_dest_pi is unsigned(7 downto 0);
subtype T_FLAGBUS_FE_DC_dest_pi is std_logic;

.....

subtype T_DATABUS_data_mem is unsigned(31 downto 0);
subtype T_FLAGBUS_data_mem is std_logic;

end package RISC_Pkg;

When I am running it with Modelsim I get the following error:

Package_LTRISC32ca_gen.vhd(355): near "package": expecting: ';'

But there is clearly a semicolon at "end package LTRISC32ca_PKG". I
havent forgotten any semicolons in between? Anyone an idea what the
issue could be?

Many thanks!

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  #2 (permalink)  
Old 11-12-2007, 04:20 PM
Sascha Frank
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Default Re: Strange VHDL Error

Sascha Frank wrote:

>
> When I am running it with Modelsim I get the following error:
>
> Package_LTRISC32ca_gen.vhd(355): near "package": expecting: ';'
>


Just found the error, I just have to leave out the package in the end
then it works.

end RISC_Pkg;

Cheers!
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  #3 (permalink)  
Old 11-12-2007, 04:32 PM
Dave
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Posts: n/a
Default Re: Strange VHDL Error

On Nov 12, 9:55 am, Sascha Frank <[email protected]> wrote:
> Hi
>
> I have a simple package that looks as follows:
>
> library IEEE;
> use IEEE.std_logic_1164.all;
> use IEEE.std_logic_arith.all;
>
> package RISC_Pkg is
>
> -- Clock type
> subtype T_clk is std_logic;
>
> -- Reset type
> subtype T_rst is std_logic;
>
> subtype T_PIPE_REG_CTRL is std_logic;
>
> subtype T_PREG_FE_DC_dest_pi is unsigned(7 downto 0);
> subtype T_FLAG_PREG_FE_DC_dest_pi is std_logic;
> subtype T_DATABUS_FE_DC_dest_pi is unsigned(7 downto 0);
> subtype T_FLAGBUS_FE_DC_dest_pi is std_logic;
>
> .....
>
> subtype T_DATABUS_data_mem is unsigned(31 downto 0);
> subtype T_FLAGBUS_data_mem is std_logic;
>
> end package RISC_Pkg;
>
> When I am running it with Modelsim I get the following error:
>
> Package_LTRISC32ca_gen.vhd(355): near "package": expecting: ';'
>
> But there is clearly a semicolon at "end package LTRISC32ca_PKG". I
> havent forgotten any semicolons in between? Anyone an idea what the
> issue could be?
>
> Many thanks!


Maybe just use "end package;" instead of "end package RISC_Pkg;"?

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  #4 (permalink)  
Old 11-12-2007, 04:47 PM
Sascha Frank
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Posts: n/a
Default Re: Strange VHDL Error


> Maybe just use "end package;" instead of "end package RISC_Pkg;"?


Thanks for your answer Dave. The problem is, that I am using Modelsim
5.7 and that I have a tool that is compatible with Modelsim 6.1.

In other words, I have to do a lot of work by hand so that it works
with the older Modelsim version.

The tool outputs

component TEST is

whereas the older Modelsim just accepts

component TEST

so there are some issiues. Anyone an idea for a workaround?
Or do I have to right a PERL script that parses me the VHDL file
and corrects it accordingly?

Many thanks!

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  #5 (permalink)  
Old 11-12-2007, 05:13 PM
HT-Lab
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Posts: n/a
Default Re: Strange VHDL Error


"Sascha Frank" <[email protected]> wrote in message
news:[email protected]
>
>> Maybe just use "end package;" instead of "end package RISC_Pkg;"?

>
> Thanks for your answer Dave. The problem is, that I am using Modelsim 5.7
> and that I have a tool that is compatible with Modelsim 6.1.
>
> In other words, I have to do a lot of work by hand so that it works
> with the older Modelsim version.
>
> The tool outputs
>
> component TEST is
>
> whereas the older Modelsim just accepts
>
> component TEST
>
> so there are some issiues. Anyone an idea for a workaround?
> Or do I have to right a PERL script that parses me the VHDL file
> and corrects it accordingly?


You are using VHDL93 syntax with VHDL87, try vcom -93 xx.vhd

Hans
www.ht-lab.com




>
> Many thanks!
>



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  #6 (permalink)  
Old 11-12-2007, 08:03 PM
Duane Clark
Guest
 
Posts: n/a
Default Re: Strange VHDL Error

HT-Lab wrote:
> "Sascha Frank" <[email protected]> wrote in message
> news:[email protected]
>>> Maybe just use "end package;" instead of "end package RISC_Pkg;"?

>> Thanks for your answer Dave. The problem is, that I am using Modelsim 5.7
>> and that I have a tool that is compatible with Modelsim 6.1.
>>
>> In other words, I have to do a lot of work by hand so that it works
>> with the older Modelsim version.
>>
>> The tool outputs
>>
>> component TEST is
>>
>> whereas the older Modelsim just accepts
>>
>> component TEST
>>
>> so there are some issiues. Anyone an idea for a workaround?
>> Or do I have to right a PERL script that parses me the VHDL file
>> and corrects it accordingly?

>
> You are using VHDL93 syntax with VHDL87, try vcom -93 xx.vhd


Or in the project.mpf file, in the [vcom] section, add or uncomment the
line:
VHDL93 = 1
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