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  #1 (permalink)  
Old 05-08-2006, 10:36 AM
zeeman_be
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Default Strange power up issue on Virtex4

Hi all,

Our PCB is showing a strange start-up/configuration issue.
The board has a virtex4 fpga (xc4vsx35-11) which gives out a DAC-clock,
configured as an LVCMOS33, fast slew rate 24 mA output driver.

Now here's the strange thing : when we configure the device through
JTAG, the clock is ok.
But when we configure it with the SAME bitstream through slave-serial
(as will be the case in the endproduct), the clock-output seems to have
slowed down significantly : slower rise/fall times, voltage swing not
reaching rail-to-rail. Then, when we do a verify through impact it says
verify=succesful, and strangely enough after this verify, our clock
output is ok again.
Note : we use ISE7.1 SP3 on a WinXP machine.

I have checked several scenarios and I am fairly sure this problem has
nothing to do with :
* signal integrity
* power levels during startup/config
* DCM lock issues

Does anyone have any clues where I could search next ? I am running out
of ideas on this.

Thanks,
Bart De Zwaef

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  #2 (permalink)  
Old 05-08-2006, 02:09 PM
Anonymous
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Default Re: Strange power up issue on Virtex4

Are you selecting the programming mode with a dip switch? If so are you sure
they are wired
correctly and not feeding one of i/o bank voltages or dcio lines or shorted
to any other pins?

Also, in the past when I had bizarre behavior like this I usually ended up
scouring through the options in "Generate Programming File". Sometimes
options that seem to be totally unrelated can have major impacts.

"zeeman_be" <[email protected]> wrote in message
news:[email protected] oups.com...
> Hi all,
>
> Our PCB is showing a strange start-up/configuration issue.
> The board has a virtex4 fpga (xc4vsx35-11) which gives out a DAC-clock,
> configured as an LVCMOS33, fast slew rate 24 mA output driver.
>
> Now here's the strange thing : when we configure the device through
> JTAG, the clock is ok.
> But when we configure it with the SAME bitstream through slave-serial
> (as will be the case in the endproduct), the clock-output seems to have
> slowed down significantly : slower rise/fall times, voltage swing not
> reaching rail-to-rail. Then, when we do a verify through impact it says
> verify=succesful, and strangely enough after this verify, our clock
> output is ok again.
> Note : we use ISE7.1 SP3 on a WinXP machine.
>
> I have checked several scenarios and I am fairly sure this problem has
> nothing to do with :
> * signal integrity
> * power levels during startup/config
> * DCM lock issues
>
> Does anyone have any clues where I could search next ? I am running out
> of ideas on this.
>
> Thanks,
> Bart De Zwaef
>



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  #3 (permalink)  
Old 05-08-2006, 02:49 PM
zeeman_be
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Posts: n/a
Default Re: Strange power up issue on Virtex4

Hi Anonymous,

the programming mode is selected with strap-resistors. I have checked
these and I am sure these are fine. This is a board we have been using
for more than 6 months now, we haven't seen any real issues on
completing the configuration phase (doen pin goes high), except for now
where it seems that right after configuration something strange happens
when the FPGA starts up with our bitstream.
I will follow your suggestion and try looking into the different bitgen
options now and hope for the best :-)

best regards,
Bart De Zwaef

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  #4 (permalink)  
Old 05-08-2006, 03:51 PM
Aurelian Lazarut
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Default Re: Strange power up issue on Virtex4

Bart,
did you change the startup clk (option in bitgen) for the two bitstreams
, you mentioned "SAME" bitstream that's why I'm asking (they supposed to
be different)
when you said "slave-serial (as will be in your end product)" I hope you
meant master-serial (unless you are using an external controller or
micro to push the bitstream) so please clarify this point.
at the first glance it looks like the part doesn't finish the config
process as it should.
what about the DONE pin?
Aurash

zeeman_be wrote:
> Hi all,
>
> Our PCB is showing a strange start-up/configuration issue.
> The board has a virtex4 fpga (xc4vsx35-11) which gives out a DAC-clock,
> configured as an LVCMOS33, fast slew rate 24 mA output driver.
>
> Now here's the strange thing : when we configure the device through
> JTAG, the clock is ok.
> But when we configure it with the SAME bitstream through slave-serial
> (as will be the case in the endproduct), the clock-output seems to have
> slowed down significantly : slower rise/fall times, voltage swing not
> reaching rail-to-rail. Then, when we do a verify through impact it says
> verify=succesful, and strangely enough after this verify, our clock
> output is ok again.
> Note : we use ISE7.1 SP3 on a WinXP machine.
>
> I have checked several scenarios and I am fairly sure this problem has
> nothing to do with :
> * signal integrity
> * power levels during startup/config
> * DCM lock issues
>
> Does anyone have any clues where I could search next ? I am running out
> of ideas on this.
>
> Thanks,
> Bart De Zwaef
>

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  #5 (permalink)  
Old 05-08-2006, 04:23 PM
zeeman_be
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Posts: n/a
Default Re: Strange power up issue on Virtex4

Hi Aurelian,

my answers :
1. we start from the same bitfile where startup-clock is set to = CCLK.
This is no problem because for JTAG configuration we use Impact or
Chipscope and these tools replace the startupclock=CCLK in our bitfile
automatically by startupclk=JTAGCLK. So apart from that different
startup-option it really is the same configuration bitstream.
2. It is slave serial configuration : we use an external controller to
program the devices.

Just to make clear : the FPGA-done pin goes high at end of config as it
should. Everything *seems* to behave normally and we have worked with
this board + fpga-config stream for several months now. No real issues
with functionality.
But now I measure my output-clock and I notice we don't have any
headroom left on our timing budget due to a supposedly slow output
driver.

I hope this clears up the situation.

Best regards,
Bart

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  #6 (permalink)  
Old 05-08-2006, 04:32 PM
Antti
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Default Re: Strange power up issue on Virtex4

the startup behaviour for slave serial and jtag is a little different,
the way the actual 'startup' sequence is sent, etc..

done=1 doesnt meant that FPGA is configured or started
it is possible that done goes high by jtag config while
1) FPGA is completly empty, no config at all
2) FPGA is loaded is corrupted bitstream
3) FPGA is loaded but not started GHIGH=0

but none of those seem to apply in your case, still check out the
bitgen options and what is maybe even better, if you have suitable
clock then use a USER clock as startup clock!

of course sending a few more CCLKs after bitstream can also fix a
problem sometimes
it is safe to stream in plain .BIT file with extra leading bulls*** and
shift in any ff's after
the actual bitstream is completed (sure not to send sync again!)

Antti
PS I did not know that ChipScope is now fixing the startup clock, a few
revisions ago it did not do that

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  #7 (permalink)  
Old 05-08-2006, 05:05 PM
zeeman_be
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Default Re: Strange power up issue on Virtex4

Antti,

I am not sure on the fixing of the startup clock by Chipscope. I just
assumed Chipscope does this, but never mentions it.
I have additional info on that and to me it makes this situation even
stranger :
When we config with Impact => Impact says it replaces CCLK by JTAGclk
=> "programming succesful", but GHIGH=0
When we config with Chipscope => chipscope does not replace CClk (?) =>
"programming succesful", and GHIGH=1.

Could this strange behaviour of the tools be related to our problem ?

Bart

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  #8 (permalink)  
Old 05-08-2006, 05:20 PM
Antti
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Default Re: Strange power up issue on Virtex4

well GHIGH is the signal that actually releases the IO enables!

but if it is not asserted properly then it usually looks like all IO
are input only, you seem to have partially/wrong enabled IOs

any if there is some mess with GHIGH then it sounds like the right
place to keep digging

Antti

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  #9 (permalink)  
Old 05-08-2006, 05:26 PM
Aurelian Lazarut
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Default Re: Strange power up issue on Virtex4

As Antti sugested, just send more clocks (cclk) from your micro to make
sure you move the configuration state machine, into a proper state.
Aurash

Antti wrote:
> the startup behaviour for slave serial and jtag is a little different,
> the way the actual 'startup' sequence is sent, etc..
>
> done=1 doesnt meant that FPGA is configured or started
> it is possible that done goes high by jtag config while
> 1) FPGA is completly empty, no config at all
> 2) FPGA is loaded is corrupted bitstream
> 3) FPGA is loaded but not started GHIGH=0
>
> but none of those seem to apply in your case, still check out the
> bitgen options and what is maybe even better, if you have suitable
> clock then use a USER clock as startup clock!
>
> of course sending a few more CCLKs after bitstream can also fix a
> problem sometimes
> it is safe to stream in plain .BIT file with extra leading bulls*** and
> shift in any ff's after
> the actual bitstream is completed (sure not to send sync again!)
>
> Antti
> PS I did not know that ChipScope is now fixing the startup clock, a few
> revisions ago it did not do that
>

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  #10 (permalink)  
Old 05-08-2006, 05:38 PM
zeeman_be
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Default Re: Strange power up issue on Virtex4

Problem is fixed !
And yes, it was the (lack of) extra CCLK cycles that was causing the
problem.

To be more precise : actually we provided about 200 CCLK-cycles of
clock activity after done goes high, but the small CPLD in between our
controller and our fpga masked this.


CPLD programming is changed, and fpga configures ok and starts up ok
with a clean fast output clock.

Thanks to all for suggestions.

best regards,
Bart

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