State Machine Trouble
 

I'm developing a state machine to read and write data into block ram.

When I make reading operation, the state is always the same, s0, and it is reassigned every time ram address changes.

The processes to detemine next_state and state operations are state sensitive. If state does not change, that processes are executed in any case?

Thanks Marco

Re: State Machine Trouble
 

Hi Marco,

if I understand you correctly your next_state generation process is of
the form
process (this_state)
begin
....
next_state <= ...

....

or the equivalent always @(this_state) in Verilog.

This is an implicit wait for an event on the signal this_state, i.e.
your process is only triggered if 'this_state' changes. If you want the
process to execute on every change to ram_address you must add
ram_address to the sensitivity list.
A possible alternative which is often used is to trigger the process on
each clock. Here the sensitivity list would look like

process (clk)
.. . . .
or even
process (clk, reset)

You can then recalculate your next_state on every clock tick in your system

Hope this helps,
Charles

Re: State Machine Trouble
 

Your state machine should reacte to any transition in the clock (rising
or falling) making it sensitive to clock change. However the reaction
nature (FSM functionality) should be according to the present state.

the clock sensitive process is usually the one that is responsible for
the state transitions (state <= next_state). if your outputs are state
dependent only (mealy machine) then you don't want them to change as
long as you stay in a specific state.

If your outputs are state and input dependent (moore machine) then you
can change your outputs (using the inputs) and still stay in the same
state. You just have to choose what kind of machine will do the trick..

Regards, Moti

Re: State Machine Trouble
 

Many Thanks to everyone!

Your help is very useful!

Marco