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  #1 (permalink)  
Old 02-13-2008, 04:49 PM
Grumps
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Posts: n/a
Default State machine outputs and tri-state

[I posted this to comp.lang.vhdl, but maybe you FPGA experts know the
answer.]

Hi
I'm not a VHDL expert, just learning, so please don't shout.

I'm using Xilinx ISE9.2sp4 and have the following code as part of a state
machine:
CP_IN_OUTPUT_DECODE: process (state_cp_in)
begin
if state_cp_in = sta_idle then
RDY <= 'Z';
BUSY <= '0';
end if;

if state_cp_in = sta_1 then
RDY <= '0';
BUSY <= '0';
end if;

if state_cp_in = sta_2 then
RDY <= '1';
BUSY <= '1';
end if;
....
....etc

The state machine goes from sta_idle, then to sta_1, then to sta_2, etc.
RDY is a pin on the device.
During operation, I can see RDY go low in sta_1, but not high in sta_2. I
know it gets to sta_2 as I can observe BUSY. I don't think RDY is tri-stated
in sta_2 as there is an external pull-up; it just stays low. Gray encoding
is used.

If I change the RDY to rdyi (signal) and then have:
RDY <= 'Z' when state_cp_in = sta_idle else rdyi;
outside of the decode process then it all behaves itself.

Apart from lack of experience, what mistake(s) have I made?
Thanks.




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  #2 (permalink)  
Old 02-13-2008, 05:49 PM
RCIngham
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Posts: n/a
Default Re: State machine outputs and tri-state

>[I posted this to comp.lang.vhdl, but maybe you FPGA experts know the
>answer.]
>
>Hi
>I'm not a VHDL expert, just learning, so please don't shout.
>
>I'm using Xilinx ISE9.2sp4 and have the following code as part of

state
>machine:
>CP_IN_OUTPUT_DECODE: process (state_cp_in)
> begin
> if state_cp_in = sta_idle then
> RDY <= 'Z';
> BUSY <= '0';
> end if;
>
> if state_cp_in = sta_1 then
> RDY <= '0';
> BUSY <= '0';
> end if;
>
> if state_cp_in = sta_2 then
> RDY <= '1';
> BUSY <= '1';
> end if;
>...
>...etc
>
>The state machine goes from sta_idle, then to sta_1, then to sta_2, etc.
>RDY is a pin on the device.
>During operation, I can see RDY go low in sta_1, but not high in sta_2

I
>know it gets to sta_2 as I can observe BUSY. I don't think RDY i

tri-stated
>in sta_2 as there is an external pull-up; it just stays low. Gra

encoding
>is used.
>
>If I change the RDY to rdyi (signal) and then have:
>RDY <= 'Z' when state_cp_in = sta_idle else rdyi;
>outside of the decode process then it all behaves itself.
>
>Apart from lack of experience, what mistake(s) have I made?
>Thanks.
>


Check that RDY is not being assigned from another process or concurren
assignment.

Check that RDY is not being assigned later in the CP_IN_OUTPUT_DECOD
process. That will take precedence.

What happens in simulation?


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  #3 (permalink)  
Old 02-13-2008, 05:59 PM
Grumps
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Posts: n/a
Default Re: State machine outputs and tri-state

"RCIngham" <[email protected]> wrote in message
news:[email protected]
> >[I posted this to comp.lang.vhdl, but maybe you FPGA experts know the
>>answer.]
>>
>>Hi
>>I'm not a VHDL expert, just learning, so please don't shout.
>>
>>I'm using Xilinx ISE9.2sp4 and have the following code as part of a

> state
>>machine:
>>CP_IN_OUTPUT_DECODE: process (state_cp_in)
>> begin
>> if state_cp_in = sta_idle then
>> RDY <= 'Z';
>> BUSY <= '0';
>> end if;
>>
>> if state_cp_in = sta_1 then
>> RDY <= '0';
>> BUSY <= '0';
>> end if;
>>
>> if state_cp_in = sta_2 then
>> RDY <= '1';
>> BUSY <= '1';
>> end if;
>>...
>>...etc
>>
>>The state machine goes from sta_idle, then to sta_1, then to sta_2, etc.
>>RDY is a pin on the device.
>>During operation, I can see RDY go low in sta_1, but not high in sta_2.

> I
>>know it gets to sta_2 as I can observe BUSY. I don't think RDY is

> tri-stated
>>in sta_2 as there is an external pull-up; it just stays low. Gray

> encoding
>>is used.
>>
>>If I change the RDY to rdyi (signal) and then have:
>>RDY <= 'Z' when state_cp_in = sta_idle else rdyi;
>>outside of the decode process then it all behaves itself.
>>
>>Apart from lack of experience, what mistake(s) have I made?
>>Thanks.
>>

>
> Check that RDY is not being assigned from another process or concurrent
> assignment.


RDY isn't assigned in another process.

> Check that RDY is not being assigned later in the CP_IN_OUTPUT_DECODE
> process. That will take precedence.


The state machine has 9 states. RDY is assigned in each state, and only
tri-stated in sta_idle. Is this wrong?
It seems to be the tri-state assignment that throws it.

> What happens in simulation?


Ah yes, simulation. As this was supposed to be a simple design, I went
straight to hardware and a scope.
Thanks.


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  #4 (permalink)  
Old 02-13-2008, 11:47 PM
Guest
 
Posts: n/a
Default Re: State machine outputs and tri-state

On Feb 14, 6:59 am, "Grumps" <[email protected]> wrote:
> "RCIngham" <[email protected]> wrote in message
>
> news:[email protected]
>
>
>
>
>
> > >[I posted this to comp.lang.vhdl, but maybe you FPGA experts know the
> >>answer.]

>
> >>Hi
> >>I'm not a VHDL expert, just learning, so please don't shout.

>
> >>I'm using Xilinx ISE9.2sp4 and have the following code as part of a

> > state
> >>machine:
> >>CP_IN_OUTPUT_DECODE: process (state_cp_in)
> >> begin
> >> if state_cp_in = sta_idle then
> >> RDY <= 'Z';
> >> BUSY <= '0';
> >> end if;

>
> >> if state_cp_in = sta_1 then
> >> RDY <= '0';
> >> BUSY <= '0';
> >> end if;

>
> >> if state_cp_in = sta_2 then
> >> RDY <= '1';
> >> BUSY <= '1';
> >> end if;
> >>...
> >>...etc

>
> >>The state machine goes from sta_idle, then to sta_1, then to sta_2, etc.
> >>RDY is a pin on the device.
> >>During operation, I can see RDY go low in sta_1, but not high in sta_2.

> > I
> >>know it gets to sta_2 as I can observe BUSY. I don't think RDY is

> > tri-stated
> >>in sta_2 as there is an external pull-up; it just stays low. Gray

> > encoding
> >>is used.

>
> >>If I change the RDY to rdyi (signal) and then have:
> >>RDY <= 'Z' when state_cp_in = sta_idle else rdyi;
> >>outside of the decode process then it all behaves itself.

>
> >>Apart from lack of experience, what mistake(s) have I made?
> >>Thanks.

>
> > Check that RDY is not being assigned from another process or concurrent
> > assignment.

>
> RDY isn't assigned in another process.
>
> > Check that RDY is not being assigned later in the CP_IN_OUTPUT_DECODE
> > process. That will take precedence.

>
> The state machine has 9 states. RDY is assigned in each state, and only
> tri-stated in sta_idle. Is this wrong?
> It seems to be the tri-state assignment that throws it.
>
> > What happens in simulation?

>
> Ah yes, simulation. As this was supposed to be a simple design, I went
> straight to hardware and a scope.
> Thanks.- Hide quoted text -
>
> - Show quoted text -


I'm saying that only because you said you were a beginner, not because
of you code .


Anyway look at a state machine, it's usually a mishmash of flipflops
and logic gates.
A tristate is usually a buffer on a bus. In hardware that's 2
different jobs.

So do something like this

1st describe a tri-state buffer something like


signal MY_BUFFER_OUT, MY_BUFFER_IN, MY_BUFFER_CONTROL : std_logic;

MY_BUFFER_OUT <= MY_BUFFER_IN when MY_BUFFER_CONTROL = '1' else 'Z';

Assign MY_BUFFER_CONTROL from your state machine, only assign 1 and 0
to RDY, connect MY_BUFFER_OUT to your port and MY_BUFFER_IN to the
equivalent of RDY.

This looks exactly the same if you think of it in software terms but
it's a different beast altogether if you take a hardware view.
I'd just like to add, I'm glad to see your using ISE, unlike the more
expensive tools it wont accept nonsense, my advice is stick with ISE
until your competent, then don't lose those good coding habbits.

Let me know how it goes Bobsterthelobster
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  #5 (permalink)  
Old 02-13-2008, 11:48 PM
Guest
 
Posts: n/a
Default Re: State machine outputs and tri-state

Sorry only half the post went :-) here it is again

Hi Grumps,

You say youre a beginner, so please allow me to offer the one piece
of advice that you should never waver from.
You are designing hardware, its not software, if you ignore that point
youll join the ranks of people that are giving the industry a bad
name with their unstable designs.
Always try to imagine the circuit youre describing, and you wontgo
far wrong.

Im saying that only because you said you were a beginner, not because
of you code .


Anyway look at a state machine, its usually a mishmash of flipflops
and logic gates.
A tristate is usually a buffer on a bus. In hardware thats 2
different jobs.

So do something like this

1st describe a tri-state buffer something like


signal MY_BUFFER_OUT, MY_BUFFER_IN, MY_BUFFER_CONTROL : std_logic;

MY_BUFFER_OUT <= MY_BUFFER_IN when MY_BUFFER_CONTROL = 1 else Z;

Assign MY_BUFFER_CONTROL from your state machine, only assign 1 and 0
to RDY, connect MY_BUFFER_OUT to your port and MY_BUFFER_IN to the
equivalent of RDY.

This looks exactly the same if you think of it in software terms but
its a different beast altogether if you take a hardware view.
Id just like to add, Im glad to see your using ISE, unlike the more
expensive tools it wont accept nonsense, my advice is stick with ISE
until your competent, then dont lose those good coding habbits.

Let me know how it goes Bobsterthelobster


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  #6 (permalink)  
Old 02-14-2008, 07:22 AM
Grumps
Guest
 
Posts: n/a
Default Re: State machine outputs and tri-state

<[email protected]> wrote in message
news:[email protected]m...
> Sorry only half the post went :-) here it is again
>
> Hi Grumps,
>
> You say youre a beginner, so please allow me to offer the one piece
> of advice that you should never waver from.
> You are designing hardware, its not software, if you ignore that point
> youll join the ranks of people that are giving the industry a bad
> name with their unstable designs.
> Always try to imagine the circuit youre describing, and you wont go
> far wrong.
>
> Im saying that only because you said you were a beginner, not because
> of you code .
>
>
> Anyway look at a state machine, its usually a mishmash of flipflops
> and logic gates.
> A tristate is usually a buffer on a bus. In hardware thats 2
> different jobs.
>
> So do something like this
>
> 1st describe a tri-state buffer something like
>
>
> signal MY_BUFFER_OUT, MY_BUFFER_IN, MY_BUFFER_CONTROL : std_logic;
>
> MY_BUFFER_OUT <= MY_BUFFER_IN when MY_BUFFER_CONTROL = 1 else Z;
>
> Assign MY_BUFFER_CONTROL from your state machine, only assign 1 and 0
> to RDY, connect MY_BUFFER_OUT to your port and MY_BUFFER_IN to the
> equivalent of RDY.
>
> This looks exactly the same if you think of it in software terms but
> its a different beast altogether if you take a hardware view.
> Id just like to add, Im glad to see your using ISE, unlike the more
> expensive tools it wont accept nonsense, my advice is stick with ISE
> until your competent, then dont lose those good coding habbits.
>
> Let me know how it goes Bobsterthelobster


Thanks for the advice and suggestions.
Your code is (similar to) what I ended up doing.

It's funny, I've been a hardware engineer for ages, and done FPGA design
with Viewdraw schematics many years ago. We now have a VHDL department, so
that's our preferred FPGA design route now. But this little project I
thought I'd do myself. It works, and only takes 22 slices of a spartan3
(there is a little more to it than this 9-state state machine).

I'm sure I'll be back here with more questions in the future.
All the best.


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  #7 (permalink)  
Old 02-14-2008, 07:31 AM
backhus
Guest
 
Posts: n/a
Default Re: State machine outputs and tri-state

Grumps schrieb:
> [I posted this to comp.lang.vhdl, but maybe you FPGA experts know the
> answer.]
>
> Hi
> I'm not a VHDL expert, just learning, so please don't shout.
>
> I'm using Xilinx ISE9.2sp4 and have the following code as part of a state
> machine:
> CP_IN_OUTPUT_DECODE: process (state_cp_in)
> begin
> if state_cp_in = sta_idle then
> RDY <= 'Z';
> BUSY <= '0';
> end if;
>
> if state_cp_in = sta_1 then
> RDY <= '0';
> BUSY <= '0';
> end if;
>
> if state_cp_in = sta_2 then
> RDY <= '1';
> BUSY <= '1';
> end if;
> ...
> ...etc
>
> The state machine goes from sta_idle, then to sta_1, then to sta_2, etc.
> RDY is a pin on the device.
> During operation, I can see RDY go low in sta_1, but not high in sta_2. I
> know it gets to sta_2 as I can observe BUSY. I don't think RDY is tri-stated
> in sta_2 as there is an external pull-up; it just stays low. Gray encoding
> is used.
>
> If I change the RDY to rdyi (signal) and then have:
> RDY <= 'Z' when state_cp_in = sta_idle else rdyi;
> outside of the decode process then it all behaves itself.
>
> Apart from lack of experience, what mistake(s) have I made?
> Thanks.
>

Hi Grumps,
you did no simulation? so how can you be sure that your FSM ever enters
sta_2 ?

If you are using an if chain instead of a case for Output decoding you
must keep in mind, that the last valid condition sets the output. even a
typo can bring you in deep trouble. A case on the other hand has a more
straightforward behavior. And the synthesis tool would complain when
conditions appear twice.

If RDY is a port there should be no problem with the 'Z' assignment.

I strongly recommend to do a simulation.

and if you like, you can try to rewrite your code like this (if applicable):

case state_cp_in is
when sta_idle => RDY <= 'Z';
BUSY <= '0';
when sta_1 => RDY <= '0';
BUSY <= '0';
when sta_2 => RDY <= '1';
BUSY <= '1';
....
end case;

Have a nice synthesis
Eilert
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  #8 (permalink)  
Old 02-14-2008, 08:14 AM
Grumps
Guest
 
Posts: n/a
Default Re: State machine outputs and tri-state

"backhus" <[email protected]> wrote in message
news:[email protected]
> Grumps schrieb:
>> [I posted this to comp.lang.vhdl, but maybe you FPGA experts know the
>> answer.]
>>
>> Hi
>> I'm not a VHDL expert, just learning, so please don't shout.
>>
>> I'm using Xilinx ISE9.2sp4 and have the following code as part of a state
>> machine:
>> CP_IN_OUTPUT_DECODE: process (state_cp_in)
>> begin
>> if state_cp_in = sta_idle then
>> RDY <= 'Z';
>> BUSY <= '0';
>> end if;
>>
>> if state_cp_in = sta_1 then
>> RDY <= '0';
>> BUSY <= '0';
>> end if;
>>
>> if state_cp_in = sta_2 then
>> RDY <= '1';
>> BUSY <= '1';
>> end if;
>> ...
>> ...etc
>>
>> The state machine goes from sta_idle, then to sta_1, then to sta_2, etc.
>> RDY is a pin on the device.
>> During operation, I can see RDY go low in sta_1, but not high in sta_2. I
>> know it gets to sta_2 as I can observe BUSY. I don't think RDY is
>> tri-stated
>> in sta_2 as there is an external pull-up; it just stays low. Gray
>> encoding
>> is used.
>>
>> If I change the RDY to rdyi (signal) and then have:
>> RDY <= 'Z' when state_cp_in = sta_idle else rdyi;
>> outside of the decode process then it all behaves itself.
>>
>> Apart from lack of experience, what mistake(s) have I made?
>> Thanks.
>>

> Hi Grumps,
> you did no simulation? so how can you be sure that your FSM ever enters
> sta_2 ?


Just a guess! All other state outputs seemed to follow my design. Only the
RDY (which was the only one with the 'Z') was errant. What I posted was a
cut-down version to make the issue clearer.

> If you are using an if chain instead of a case for Output decoding you
> must keep in mind, that the last valid condition sets the output. even a
> typo can bring you in deep trouble. A case on the other hand has a more
> straightforward behavior. And the synthesis tool would complain when
> conditions appear twice.


Yes, using an if chain. I can't see any typos, and all state conditions are
tested.

> If RDY is a port there should be no problem with the 'Z' assignment.


RDY's an inout port.

> I strongly recommend to do a simulation.


I will. Not to check my design, which now works, but to see how the
simulator works.

> and if you like, you can try to rewrite your code like this (if
> applicable):
>
> case state_cp_in is
> when sta_idle => RDY <= 'Z';
> BUSY <= '0';
> when sta_1 => RDY <= '0';
> BUSY <= '0';
> when sta_2 => RDY <= '1';
> BUSY <= '1';
> ...
> end case;


I will try that. Should only take a few minutes.

> Have a nice synthesis


Thanks


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  #9 (permalink)  
Old 02-14-2008, 09:33 AM
Grumps
Guest
 
Posts: n/a
Default Re: State machine outputs and tri-state

"Grumps" <[email protected]> wrote in message
news:[email protected]
> "backhus" <[email protected]> wrote in message
> news:[email protected]
>> Grumps schrieb:

[ snipped ]
>> and if you like, you can try to rewrite your code like this (if
>> applicable):
>>
>> case state_cp_in is
>> when sta_idle => RDY <= 'Z';
>> BUSY <= '0';
>> when sta_1 => RDY <= '0';
>> BUSY <= '0';
>> when sta_2 => RDY <= '1';
>> BUSY <= '1';
>> ...
>> end case;

>
> I will try that. Should only take a few minutes.


I replaced my original process based on lots of if <state> = <blah>, with
the case method (above). It works!
I don't fully understand why though.
I simply replaced the "if state_cp_in = " with "when" in my original code so
any typos would be preserved.


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