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Old 04-19-2004, 02:16 PM
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Default SRAM Controller

Dear Sir or Madam,

I have some problems with implementing an SRAM controller.
At http://mitglied.lycos.de/vazquez78 (link SRAM Controller) there are shown
some plots.

My question:

As you can see the control sequence is WRITE READ NOP WRITE READ NOP ...
(clock period : 11.11ns)

When I go from WRITE to READ
OE_n becomes active whereas WE_n becomes inactive at
the same time.
(Note: In simulation assertion / deassertion of control signals etc. is
delayed by one clock cycle with regard to the state name ! )

The simulation shows that the read data are not correct.

What does go wrong? Is the control sequence not right that is
asserting OE_n and deasserting WE_n at the same time is not allowed?

Thank you very much for your help.

Kind regards
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  #2 (permalink)  
Old 04-22-2004, 08:29 AM
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Default Re: SRAM Controller


please have a look at my homepage again.
I've put some additional colors in the plot to make it more clear.
Hope that helps to understand the problem.

I would appreciate your time and help.

Kind regards
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