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Old 10-26-2007, 11:10 AM
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Default "SPI indirect" programming for any FPGA/CPLD


attached to xilinx forum message


is a simple JTAG-SPI gateway IP core that is been used for SPI flash
programming on S3E
the demo toplevel include Spartan-3 BSAN, but by only replacing that
primitive it is adaptable
to almost any FPGA/CPLD family


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