FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > FPGA

FPGA comp.arch.fpga newsgroup (usenet)

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 10-29-2005, 06:16 PM
Raymund Hofmann
Guest
 
Posts: n/a
Default Spartan3 DFS & DLL Behaviour

Using the DFS to multiply a clock leaves some questions for me:

The data specifies cycle-to-cycle jitter & period jitter at the input.

A period jitter of +-1 ns seems not plausible to me.
From what ideal clock edge is the +-1ns specified ?
From the clock specified in the clocking wizard ?
Is the clock frequency specified there getting into the device
configuration ?
For a 50ns period input +1ns is +2%.
This isn't plausible to me as timing of the device changes more than 2%
with temperature and supply voltage.

The question is rather:

How would the DFS track a changing input frequency (and device
temperature variations and device supply voltage variations of course)?
Is there a limit on the speed of this change, before the DFS "unlocks" ?
+-1ns per input clock period ?

For Example a input clock

25ns period, switching to 24ns period in one cycle

A "traditional" PLL with Phase comparator, loop filter & vco has a loop
bandwidth, determining the speed of tracking.
So it's behaviour would be some kind of step response of the output
frequency.

How would the DFS behave ?
Can the DFS be used to multiply a clock coming from a variable source ?
What's the tracking speed (loop bandwidth)?

Raymund Hofmann

Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
Incorrect behaviour of a non-blocking assignment. [email protected] Verilog 6 05-19-2006 05:39 AM
FPGA behaviour when its used resource is >90% ? [email protected] FPGA 8 10-10-2005 08:55 AM
crazy behaviour of fpga, timing ? Alexander Korff FPGA 12 05-12-2005 12:12 AM
strange behaviour of the design sameer FPGA 3 05-23-2004 11:27 PM


All times are GMT +1. The time now is 12:53 AM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved