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Old 04-26-2006, 12:20 PM
Dave
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Default Spartan 3E Starter Board Question

I have never done an FPGA design and I am considering purchasing the
Starter Board. It has crossed my mind to implement at least part of a
design I did in an ASIC many years ago. The largest part of the ASIC
design was a "funnel" shifter. Basically the shifter operated as a barrel
shifter on the 96-bit input and output the 21-bits beginning at any
designated position. Cycle time was one clock.

Is this doable with the XC3500 on the Starter Board? How much of the
logic would this consume? Any thoughts on what the max clock rate would
be?


Thanks!

~Dave~
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Old 04-26-2006, 05:11 PM
John_H
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Default Re: Spartan 3E Starter Board Question

"Dave" <[email protected]> wrote in message
news[email protected]
>I have never done an FPGA design and I am considering purchasing the
> Starter Board. It has crossed my mind to implement at least part of a
> design I did in an ASIC many years ago. The largest part of the ASIC
> design was a "funnel" shifter. Basically the shifter operated as a barrel
> shifter on the 96-bit input and output the 21-bits beginning at any
> designated position. Cycle time was one clock.
>
> Is this doable with the XC3500 on the Starter Board? How much of the
> logic would this consume? Any thoughts on what the max clock rate would
> be?
>
>
> Thanks!
>
> ~Dave~


With almost no effort to speed the process you can easily achieve 85 MHz
with 261 LUTs (2% of the XC3S500E-4) giving you a full 0-127 rotate of a
96-bit vector with 21 bits out. If you replicate some select bits you can
improve on the timing. If you pipeline the operation, you can do better
still.

module
funnel
( input clk
, input [95:0] large_word
, input [ 6:0] select
, output [20:0] selected
);

reg [ 6:0] s;
reg [20:0] selected;

always @(posedge clk) s <= select;

wire [147:0] s4 = {large_word[51:0],large_word};
wire [ 51:0] s3 = s4 >> (s & 7'h60);
wire [ 27:0] s2 = s3 >> (s & 7'h18);
wire [ 21:0] s1 = s2 >> (s & 7'h06);
wire [ 20:0] s0 = s1 >> (s & 7'h01);

always @(posedge clk) selected <= s0;

endmodule


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