First, I will disclose that I work for Altera. My advice is to try the
comparisons yourself and you will find out which family is best for
you.
Altera has made it very easy to verify power consumption claims
yourself using the Cyclone III
FPGA Starter Kit. It provides an
application note and circuitry to easily measure Cyclone III
FPGA
static and dynamic power consumption.
http://www.altera.com/products/devki...3-starter.html.
You can also purchase the EP3C120 device for measurement using your
own board. A board including the largest Cyclone III EP3C120 is in
development.
In the interest of providing both sides of the story I will provide
some responses to the claims below.
On Aug 21, 8:12 am, austin <
[email protected]> wrote:
> Manny,
>
> Request the C3 vs S3A power comparison slides from your FAE.
>
> To me, while running (dynamic + static), it seems to be a wash (roughly
> equal, with S3A slightly better).
Using the power estimator results from both vendors does not
substantiate this claim. For example, looking at static power only,
The Cyclone III EP3C120 has roughly 119K logic elements and 3,888 kits
of memory while its static power consumption is just 0.169 whether it
is active or suspended.
The Xilinx XC3SD3400A has 23,872 slices which is roughly equivalent to
just 48K logic elements and has 2268 kbits of memory. Static power for
the low power version of this part in active mode is 0.451W. In
suspend mode it drops to 0.234W while the part is suspended.
These comparisons used the latest versions of both spreadsheet
estimators and assume 85C junction temperature and still air.
> When not running, S3A has power savings modes, so it is a clear winner
> if you decide to use one or both of the modes).
Altera devices include an ALTCLKCNTRL function that can be used to
shut off clock networks to lower power consumption. Altera users are
not penalized with higher static power consumption when the clocks
resume operation. This function provides fine grained control over
what is shut on/off and how much power savings is achieved. You can
shut down the whole part or just selected functions/clocks which
provides a lot of flexibility.
> Of course, it isn't hard to create a design where one, or the other
> shows an advantage for dynamic+static power. This slide set attempts to
> have a apples to apples comparison: you judge how careful we were to
> make things "the same."
> In general, the 90nm node for medium performance transistors is less
> leaky (less static power), and also has more dynamic power than 65nm.
>
> 65nm is generally leakier, unless performance is lessened by increasing
> the Vt's of the core transistors. In fact, at 65nm, even the gates leak
> (this static current is independent of temperature).
In general these statements are true if nothing is done to mitigate
these issues. However, the Altera Cyclone III architecture is built on
TSMC's low power process and uses an intelligent selection of low Vt's
for fast performance only where speed critical. In non-speed critical
circuits slower, higher Vt transistors are used. Altera also uses low
Vt transistors coupled with longer channel lengths to get a balance
between good performance and low leakage.
> The steepness of the increase in static current of 65nm is much greater
> than at 90nm with increasing junction temperature. Be sure to use a die
> temperature that is in keeping with your real application.
>
> Austin
The proof is in the pudding. Regardless of what Austin or I say,
perform your own comparisons and I am confident you will be impressed
by the combination of relatively higher performance, higher
functionality, and lower power consumption Cyclone III FPGAs deliver.
Regards,
Rob