FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal


Go Back   FPGA Groups > NewsGroup > FPGA

FPGA comp.arch.fpga newsgroup (usenet)

LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 01-20-2004, 01:46 PM
Kelvin @ SG
Posts: n/a
Default Small bit manipulation on two designs with routing differences...

Hi, everybody:

I have two similar designs the only difference is filtering(involving
registers and logic differences),
while the rest are same...Now I P& R them with the same guide file
containing the fixed portion...

If I do a bitgen to generate the difference bitstream of these two routed
designs, will it work on
hardware? The BitGen allows me to generate a 1kb bitstream...while the fixed
logic is 100kb+...

The wording in the XAPP290 is "not recomended", but does the contention
cause temporarily
mulfunction in the logic (which can be recovered with my design) or will the
contention burn the
FPGA chip?

Thanks for your advice.

Reply With Quote


Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On

Similar Threads
Thread Thread Starter Forum Replies Last Post
What is the differences between a assertion vip and a tranditional vip? samuel Verilog 0 06-25-2007 09:18 AM
Manipulation on netlist for faster simulation. Kelvin Verilog 11 08-09-2004 05:22 PM
PLI .so linking, libtool and simulator differences Peter Riocreux Verilog 7 09-04-2003 09:22 AM
What's the differences between translation_* and synthesis_*(Synopsys)? Peng Yu Verilog 2 08-13-2003 05:56 AM

All times are GMT +1. The time now is 12:45 AM.

Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved