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Old 10-30-2003, 02:48 PM
Valentin Tihomirov
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Default simulation stops preliminarily

this code causes 100% simulation failure.

Rx <= '1'; wait for 1 * BIT_TIME; -- initialize a bit value

assert (Rx = '0') -- fail if bit = '1'
report "Invalid data received1!"
severity failure;

assert (Rx = '1') -- fail if bit = '0'
report "Invalid data received2!"
severity failure;

wait until AVAIL = '1';

wait; -- will wait forever





I need to check a vaue after AVAIL rises to '1'. But the following test
shows that simulator ignores ASSERT clauses placed between WAIT forever
statement.

Rx <= '1'; wait for 1 * BIT_TIME; -- initialize a bit value

wait until AVAIL = '1'; -- wait for condition


-- these assertions are ignored by simulator!

assert (Rx = '0') -- fail if bit = '1'
report "Invalid data received1!"
severity failure;

assert (Rx = '1') -- fail if bit = '0'
report "Invalid data received2!"
severity failure;

wait; -- will wait forever




Does ModelSim behaves properly?


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  #2 (permalink)  
Old 10-30-2003, 05:14 PM
Jonathan Bromley
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Default Re: simulation stops preliminarily

"Valentin Tihomirov" <[email protected]> wrote in
message news:[email protected]

> I need to check a vaue after AVAIL rises to '1'. But the following test
> shows that simulator ignores ASSERT clauses placed between WAIT forever
> statement.
>
> Rx <= '1'; wait for 1 * BIT_TIME; -- initialize a bit value
>
> wait until AVAIL = '1'; -- wait for condition
>
>
> -- these assertions are ignored by simulator!
>
> assert (Rx = '0') -- fail if bit = '1'
> report "Invalid data received1!"
> severity failure;
>
> assert (Rx = '1') -- fail if bit = '0'
> report "Invalid data received2!"
> severity failure;
>
> wait; -- will wait forever


Are you 100% sure that AVAIL is making a transition to '1'
at some time after the previous wait has finished?

Don't forget that "wait until" is EDGE triggered. It
will wait forever if AVAIL is stuck at '1'.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
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Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
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The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.



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  #3 (permalink)  
Old 11-01-2003, 07:28 PM
Jim Lewis
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Default Re: simulation stops preliminarily

>>I need to check a vaue after AVAIL rises to '1'.

> Don't forget that "wait until" is EDGE triggered. It
> will wait forever if AVAIL is stuck at '1'.


And to add to what Jonathan said, if you want to do a
level check, do the following:

if (Avail /= '1') then
wait until AVAIL = '1';
end if ;


Read wait as stop.
Wait always stops for at least one delta cycle.

Cheers,
Jim
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~
Jim Lewis
Director of Training mailto:[email protected]
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~

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