FPGA Central

Is there any way to speed up simulation (functional or timing) when
simulating a Xilinx FPGA which uses the DCM? The DCM requires that the
simulator resolution be set to ps range and this really slows down the
simulation speed. I have reduced time delays in my design to reduce
the simulation time required, however it still takes about 1 hour per
millisecond of simulation time. Other than getting a faster computer
are there any other things that can be done to reduce the simulation
time? I have already removed high frequency signals (clocks) from the
simulator waveform window and used variables where possible.

Nick Suttora wrote:

> the simulation time required, however it still takes about 1 hour per
> millisecond of simulation time. Other than getting a faster computer
> are there any other things that can be done to reduce the simulation
> time? I have already removed high frequency signals (clocks) from the
> simulator waveform window and used variables where possible.


Consider siming your source level before gate level.
That's about ten times faster.

-- Mike Treseler

Mike Treseler <[email protected]> wrote in message news:<[email protected]>...
> Nick Suttora wrote:
>
> > the simulation time required, however it still takes about 1 hour per
> > millisecond of simulation time. Other than getting a faster computer
> > are there any other things that can be done to reduce the simulation
> > time? I have already removed high frequency signals (clocks) from the
> > simulator waveform window and used variables where possible.
>
>
> Consider siming your source level before gate level.
> That's about ten times faster.
>
> -- Mike Treseler

I am using a core in the part which was delivered as a gate level
netlist so I have no choice.

Nick Suttora wrote:

>>Consider siming your source level before gate level.
>>That's about ten times faster.
>>
>> -- Mike Treseler
>
>
> I am using a core in the part which was delivered as a gate level
> netlist so I have no choice.

The choice is a tradeoff of the cost of getting the source
code vs the cost of testing the core netlist as is.

-- Mike Treseler