FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > FPGA

FPGA comp.arch.fpga newsgroup (usenet)

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 01-13-2004, 01:51 PM
Amontec Team, Laurent Gauch
Guest
 
Posts: n/a
Default simulating xilinx clkdll

Hi,

I have some troubles simulating a clkdll primitive with modelsim.

I included a clkdll mapping in my VHDL project to do a clk2x and clk4x.
After synthesis, all is working fine about frequency value (I have a 40
- 80 - 160 MHz).

But now I have to simulate all of this with the main design.
BUT how can I simulate CLKDLL without body description of the unisim
library.

For now, I just did a new VHDL architecture for my CLKDLL. But are there
a better solution for simulation!

Best Regards,
Laurent Gauch


------------ And now a word from our sponsor ------------------
Do your users want the best web-email gateway? Don't let your
customers drift off to free webmail services install your own
web gateway!
-- See http://netwinsite.com/sponsor/sponsor_webmail.htm ----
Reply With Quote
  #2 (permalink)  
Old 01-14-2004, 09:53 AM
???
Guest
 
Posts: n/a
Default Re: simulating xilinx clkdll

Hi, May be you didn't compile libruary....

If you have ise 5.2 or over then #15338 in Xilinx support...

You can find compxlib.

I can't english...sorry ^^*

Good luck...bye

"Amontec Team, Laurent Gauch" <[email protected]> wrote
in message news:[email protected]
> Hi,
>
> I have some troubles simulating a clkdll primitive with modelsim.
>
> I included a clkdll mapping in my VHDL project to do a clk2x and clk4x.
> After synthesis, all is working fine about frequency value (I have a 40
> - 80 - 160 MHz).
>
> But now I have to simulate all of this with the main design.
> BUT how can I simulate CLKDLL without body description of the unisim
> library.
>
> For now, I just did a new VHDL architecture for my CLKDLL. But are there
> a better solution for simulation!
>
> Best Regards,
> Laurent Gauch
>
>
> ------------ And now a word from our sponsor ------------------
> Do your users want the best web-email gateway? Don't let your
> customers drift off to free webmail services install your own
> web gateway!
> -- See http://netwinsite.com/sponsor/sponsor_webmail.htm ----



Reply With Quote
  #3 (permalink)  
Old 01-14-2004, 10:51 PM
Amontec Team, Laurent Gauch
Guest
 
Posts: n/a
Default Re: simulating xilinx clkdll

Thanks ??? for this advice

??? wrote:
> Hi, May be you didn't compile libruary....
>
> If you have ise 5.2 or over then #15338 in Xilinx support...
>
> You can find compxlib.
>
> I can't english...sorry ^^*
>
> Good luck...bye
>
> "Amontec Team, Laurent Gauch" <[email protected]> wrote
> in message news:[email protected]
>
>>Hi,
>>
>>I have some troubles simulating a clkdll primitive with modelsim.
>>
>>I included a clkdll mapping in my VHDL project to do a clk2x and clk4x.
>>After synthesis, all is working fine about frequency value (I have a 40
>>- 80 - 160 MHz).
>>
>>But now I have to simulate all of this with the main design.
>>BUT how can I simulate CLKDLL without body description of the unisim
>>library.
>>
>>For now, I just did a new VHDL architecture for my CLKDLL. But are there
>> a better solution for simulation!
>>
>>Best Regards,
>>Laurent Gauch
>>
>>
>>------------ And now a word from our sponsor ------------------
>>Do your users want the best web-email gateway? Don't let your
>>customers drift off to free webmail services install your own
>>web gateway!
>>-- See http://netwinsite.com/sponsor/sponsor_webmail.htm ----

>
>
>


Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
simulating Xilinx cores FPGA Verilog 0 03-13-2008 10:27 PM
EDK 3.2: timing constraint for CLKDLL Heiko Panther FPGA 0 09-22-2003 12:59 PM
using CLKDLL, want: myclock <= CLKDV and LOCKED Ben Gerblich FPGA 0 08-31-2003 03:17 PM


All times are GMT +1. The time now is 01:14 PM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2021, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved