FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > FPGA

FPGA comp.arch.fpga newsgroup (usenet)

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 04-11-2006, 01:25 AM
Jon
Guest
 
Posts: n/a
Default Simulating TFT core in EDK

I'm trying to use the TFT IP core provided by Xilinx and am unable to
simulate the entire system using ModelSim 6.1e. I've compiled the EDK
and ISE libraries correctly, and I'm simply trying to find a way to let
my verilog files know where to find the necessary files. When
compiling the TFT piece, I receive the following error messages:

# ** Error: (vsim-3033)
C:/vga_dcr_ddr/pcores/plb_tft_cntlr_ref_v1_00_d/hdl/verilog/plb_tft_cntlr_ref.v(501):
Instantiation of 'BUFG' failed. The design unit was not found.
# Region: /system/vga_framebuffer/vga_framebuffer/BUFG_pixclk
# Searched libraries:
# plb_tft_cntlr_ref_v1_00_d
# ** Error: (vsim-3033)
C:/vga_dcr_ddr/pcores/plb_tft_cntlr_ref_v1_00_d/hdl/verilog/plb_tft_cntlr_ref.v(526):
Instantiation of 'DCM' failed. The design unit was not found.
# Region: /system/vga_framebuffer/vga_framebuffer/DCM_pixclk
# Searched libraries:
# plb_tft_cntlr_ref_v1_00_d

The only thing I can think to do would be to copy the BUFG and DCM
components from the ISE library into the simulation directory so that
the compiler can find them. But, in order to do that, I think I need
to modify the _info file that sits in the root directory to indicate
that those files are there.

Are there any other steps that I'm missing?

Reply With Quote
  #2 (permalink)  
Old 04-11-2006, 03:01 AM
johnp
Guest
 
Posts: n/a
Default Re: Simulating TFT core in EDK

Are you including the unisims directory in the verilog simulation with
a -y option? You need to tell Verilog where the models for the BUFG
and the DCM live.

John Providenza

Reply With Quote
  #3 (permalink)  
Old 04-11-2006, 03:17 AM
Jon
Guest
 
Posts: n/a
Default Re: Simulating TFT core in EDK

I'm assuming by that I need to put the -y option in the system.do file
that gets generated by the EDK...

If so, I'll try it and see what I can come up with. Thanks.

Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
Simulating PLB DDR in EDK 7.1 SP2 using ModelSim 6.0a Nju Njoroge FPGA 2 11-24-2005 04:09 AM
Simulating Cyclone II PLL Mark McDougall FPGA 2 11-02-2005 07:58 AM
simulating chuk FPGA 1 01-19-2004 05:53 PM


All times are GMT +1. The time now is 09:43 AM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved