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Old 01-05-2006, 01:09 PM
Posts: n/a
Default Simulating EDIF from DK with Xilinx ISE waveform analyzer

Dear all:

When I generate an EDIF from Handel-C in DK3.1, I want simulate it with
Xilinx ISE waveform analyzer, but always the output signals appear with
the "U" (undefined) value (I test it creating a schematic symbol from
EDIF with the edif2sym tool). This problem also exists using modelsim
waveform analyzer.

With older Xilinx Foundation 4 this problem doesn't appear (in this
version, the schematic symbol is generated from EDIF as menu option in
the schematic tools).

For example, I've used the following code for testing purposes:

/**** Xilinx Virtex V2000E-6/7/8-BG560 ****/
set clock = external_divide 3;
unsigned int 1 x_init;
interface bus_in (unsigned int 1) init()
with {data={"A27"}};
unsigned int 5 x_result;
interface bus_out () result (unsigned int 5 OutPort=x_result)
with {data={"B25","C28","C30","D30","A3"}};
unsigned int 1 x_end;
interface bus_out () end (unsigned int 1 OutPort=x_end)
with {data={"D9"}};
void Algorithm(void) {
unsigned int 5 cont;
cont = 0;
while(cont<15) {
void main(void)
if(x_init==0) {
else {

Does anybody have the same problem? Can anybody help me?
Thanks a lot.

Best regards,

Juan A.
University of Extremadura

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