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Old 01-19-2004, 04:55 PM
chuk
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Default simulating

Hello, I am relatively new to Xilinx and VHDL programming for that
matter. I have currently concluded certain sections of my final
design, however I need to test it by imposing signals at inputs to
this design. Currently I have had to design vhdl parts that would
generate these signals however I would like to these to not be
synthesised with the rest of the design. Is there any method by which
I can impose more complex signals on the testbench or modelsim?
Thanks
C
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Old 01-19-2004, 05:53 PM
Mike Treseler
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Default Re: simulating

chuk wrote:
> Hello, I am relatively new to Xilinx and VHDL programming for that
> matter. I have currently concluded certain sections of my final
> design, however I need to test it by imposing signals at inputs to
> this design. Currently I have had to design vhdl parts that would
> generate these signals however I would like to these to not be
> synthesised with the rest of the design. Is there any method by which
> I can impose more complex signals on the testbench or modelsim?


Modelsim is your simulator.
A testbench is a text file: a vhdl architecture.
containing an instance of your uut entity code.
A testbench process can generate any waveform you like,
either algorithmically or from a table.

Poke around in here to clarify your question.
http://groups.google.com/groups?q=tr...tbench+example

-- Mike Treseler

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