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  #1 (permalink)  
Old 07-27-2005, 05:54 PM
pasacco
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Default simulatable but not synthesizable (verifiable)

Dear

I am synthesizing and mapping following examples (counters) into Vertex
II pro with ISE6.3. Both of them are working okay in Modelsim.

And I wish to verify them after mapping using Chipscope Pro - Inserter
and Analyzer.

Version 1 is okay.

Version 2 is a version, which has "rst" input signal. Problem is that
version 2 not okay in ChipScope Pro, saying that " INFO - Device 2 Unit
0: Waiting for core to be armed ".

Both of them are error-free and warning-free during mapping process.
What is the problem in version 2? Is it really a problem? How can we
verify the version 2?

Thankyou again Regards


----- Version 1 ----------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity top is
port
(
clk : in std_logic := '0';
cnt : out std_logic_vector(3 downto 0)
);
end top;

architecture behave of top is
signal counter : std_logic_vector(31 downto 0):= (others => '0');
begin
process(clk)
begin
if ( clk'event and clk = '1' ) then
counter <= counter + 1;
end if;
end process;

cnt <= counter(31 downto 28);

end behave;

------- Version 2 -----------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity top is
port
(
clk : in std_logic;
rst : in std_logic ; -- additional 'rst' input
cnt : out std_logic_vector(3 downto 0)
);
end top;

architecture behave of top is
signal counter : std_logic_vector(31 downto 0):= (others => '0');
signal rst_tmp: std_logic;

begin

rst_tmp <= rst;

process(clk)
begin

if rst_tmp='1' then
counter <= (others => '0');
elsif ( clk'event and clk = '1' ) then
counter <= counter + 1;
end if;
end process;

cnt <= counter(31 downto 28);

end behave;
-----------------------------------------------------

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  #2 (permalink)  
Old 07-27-2005, 06:15 PM
Jonathan Bromley
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Default Re: simulatable but not synthesizable (verifiable)

On 27 Jul 2005 08:54:11 -0700, "pasacco" <[email protected]> wrote:

>version 2 not okay in ChipScope Pro, saying that " INFO - Device 2 Unit
>0: Waiting for core to be armed ".


I don't understand this because I don't know about ChipScope Pro,
but I do understand why your VHDL is wrong.

>process(clk)
>begin
> if rst_tmp='1' then
> counter <= (others => '0');
> elsif ( clk'event and clk = '1' ) then
> counter <= counter + 1;
> end if;
>end process;


rst_tmp is required to reset the counter on both rising
and falling edges of the clock. This is clearly inappropriate
for any real devices.

>Both of them are error-free and warning-free during mapping process.


This is strange - the synthesis tool should reject it,
or at least issue a warning for the incorrect coding style.

>What is the problem in version 2? Is it really a problem?


If you want the reset to be synchronous, put it into the
clocked-logic part of the process so that it is tested
synchronously:

process(clk)
begin
if ( clk'event and clk = '1' ) then
if rst_tmp = '1' then
counter <= (others => '0');
else
counter <= counter + 1;
end if;
end if;
end process;

If you want the reset to be asynchronous, put it in the
sensitivity list and test it asynchronously:

process(clk, rst_tmp)
begin
if rst_tmp='1' then
counter <= (others => '0');
elsif ( clk'event and clk = '1' ) then
counter <= counter + 1;
end if;
end process;
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:[email protected]
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
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  #3 (permalink)  
Old 07-27-2005, 07:14 PM
Gunther Mannigel
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Posts: n/a
Default Re: simulatable but not synthesizable (verifiable)

Jonathan Bromley schrieb:
>
>>process(clk)
>>begin
>> if rst_tmp='1' then
>> counter <= (others => '0');
>> elsif ( clk'event and clk = '1' ) then
>> counter <= counter + 1;
>> end if;
>>end process;

>
>
> rst_tmp is required to reset the counter on both rising
> and falling edges of the clock. This is clearly inappropriate
> for any real devices.


It is an asynchronous reset. I think he should have rst_tmp in
the sensitivity list.

cheers
Gunther
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  #4 (permalink)  
Old 07-27-2005, 07:42 PM
pasacco
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Posts: n/a
Default Re: simulatable but not synthesizable (verifiable)

Yes, I missed it. Reset signal "rst_tmp" should be within sensitivity
list. Below is the correct one.

BTW, my goal is to "verify" its functionality (of the "internal" 32 bit
counter) in a real FPGA chip.

In version 1, I am able to "see" the behavior of internal signals in
waveform (exactly same as simulation), using "Inserter" and "Analyzer"
in ChipScope Pro.
The difference between version 1 and 2 is the 'rst' input signal.
In version 2, however, no waveform can be seen in "Analyzer". That was
a problem

If someone has idea how to set up ChipScope Pro environment for this
case, let me know.

Thankyou so much. Regards

------- Version 2 ------------------------------*-----
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity top is
port
( clk : in std_logic;
rst : in std_logic ; -- additional 'rst' input
cnt : out std_logic_vector(3 downto 0) );
end top;

architecture behave of top is
signal counter : std_logic_vector(31 downto 0):= (others => '0');
signal rst_tmp: std_logic := '0'; -- initialization
begin
rst_tmp <= rst;
process(rst_tmp,clk)
begin
if rst_tmp='1' then
counter <= (others => '0');
elsif ( clk'event and clk = '1' ) then
counter <= counter + 1;
end if;
end process;
cnt <= counter(31 downto 28);
end behave;
------------------------------*-----------------------

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