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07-03-2004, 09:00 AM

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A simple VHDL question

Could anyone explain what is the meaning of

out0 <= (others => '0');

in the following VHDL code.

if reset = '1' then
out0 <= (others => '0');
out1 <= (others => '0');
else
out0 <= in0;
out1 <= in1;
end if;

Thanks,

Jay

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