FPGA Central

I am a newbie in Xilinx FPGA and am trying to prototype my own
architecture. I tried the tutorial about stopwatch. Everything is OK.

Then I tried a simple design "3-bit counters". The behavioral model and
translate model works. But the post-map model doesn't work. I don't
know why?

Here I did't use DCM. I have the clk pin feed to my counter directly.
Could this cause a problem?Thanks,

Dear All,

After I take a look at the schematic view of post-map RTL code, it
seems "reset" signal is connected to the "clk" of FF and "clk" signal
is connected to the "reset" of FF. What is wrong there?How can I fix
this problem?Thanks,

You need a better description than this in order for someone to help.
You might want to consider sending the VHDL or verilog.
but you probably haven't coded it correctly with the right 'always @
(posedge clk)'

Simon


<[email protected]> wrote in message
news:[email protected] oups.com...
> Dear All,
>
> After I take a look at the schematic view of post-map RTL code, it
> seems "reset" signal is connected to the "clk" of FF and "clk" signal
> is connected to the "reset" of FF. What is wrong there?How can I fix
> this problem?Thanks,
>

Hello,

Could you paste your code? This would help us to determine the problem
(which, according to your description is the code)

Vladislav

<[email protected]> wrote in message
news:[email protected] oups.com...
> Dear All,
>
> After I take a look at the schematic view of post-map RTL code, it
> seems "reset" signal is connected to the "clk" of FF and "clk" signal
> is connected to the "reset" of FF. What is wrong there?How can I fix
> this problem?Thanks,
>