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Old 10-20-2003, 12:47 AM
Panic
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Default Several Quartus II 3.0 questions


I'm a student working an a Altera EPXA1F484C1 FPGA, and I'm having some
problems I hope someone can help me with.

1. Is there a way to tell Quartus that the project I'm compiling is ment as
a "internal" building block, meaning that the pins isn't actual device pins,
but "internal pins"? I'm wondering since I have several "internal blocks"
with 128 bits in and out, and Quartus stops my compilings complaining that
the device I'm compiling for has to few pins for my design.

2. I get stuck-at errors...and I have no idea why. I get this warning:
"Warning: No clock transition on AESRoundSP-
2:inst|lpm_dff0:inst5|lpm_ff:lpm_ff_component|dffs[127] register"
And this continues for all 128 flipflops. But they are clocked by the
"master clock". I have not created a clock signal, but the clock is named
clk, and then Quartus should assume that the signal is a clock, right?
Anyway, Quartus compiles my design without errors, but the summary tells me
that I'm not using any LEs or any memory bits...

The AESRoundSP-2 is a building block in a larger design, but does not
compile "on its own" because it uses too many pins and memory bits. Can this
cause the weird error in (2)?


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  #2 (permalink)  
Old 10-20-2003, 02:52 AM
Subroto Datta
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Default Re: Several Quartus II 3.0 questions

There is a way to tell Quartus that certain pins are not actual pins, and
they should not count towards the I/O count. You do that my marking them
with the Assignment called Virtual Pins. Follow these steps.

1. Compile the design through Analysis and Synthesis.
2. Open the Assignment Editor.
3. Select the Logic Options Button on the top.
4. Enter the pin name you want under Destination Name.
5. Select the Logic Option under Option.
5. Set the Value to On.

When you compile the design it should reduce the number of primary
inputs/outputs by the number of virtual pins.
----------------------------------------------------------------------------
---------------------------------

Quartus can infer clocks by analyzing signals which directly drive the clock
input of registers. However to make a frequency assignment to a clock signal
you first need to define

Step A. A New Clock Setting using the Assignment->Timing
Settings->Clocks->New Clock Settings. The next step is to assign this clock
setting to a clock signal. You do this by:

Step B:
1. Compile the design through Analysis and Synthesis.
2. Open the Assignment Editor.
3. Select the Timing Button on the top.
4. Enter the pin name you want under Destination Name.
5. Select the Clock Settings under Option.
5. Set the Value to the name of the setting you created in Step A.

In general when you see an error message, you can click on the message and
hit F1 for help, to see the Cause and Possible Actions that you can take.

- Subroto Datta
Altera Corp.






"Panic" <[email protected]> wrote in message
news:[email protected]
>
> I'm a student working an a Altera EPXA1F484C1 FPGA, and I'm having some
> problems I hope someone can help me with.
>
> 1. Is there a way to tell Quartus that the project I'm compiling is ment

as
> a "internal" building block, meaning that the pins isn't actual device

pins,
> but "internal pins"? I'm wondering since I have several "internal blocks"
> with 128 bits in and out, and Quartus stops my compilings complaining that
> the device I'm compiling for has to few pins for my design.
>
> 2. I get stuck-at errors...and I have no idea why. I get this warning:
> "Warning: No clock transition on AESRoundSP-
> 2:inst|lpm_dff0:inst5|lpm_ff:lpm_ff_component|dffs[127] register"
> And this continues for all 128 flipflops. But they are clocked by the
> "master clock". I have not created a clock signal, but the clock is named
> clk, and then Quartus should assume that the signal is a clock, right?
> Anyway, Quartus compiles my design without errors, but the summary tells

me
> that I'm not using any LEs or any memory bits...
>
> The AESRoundSP-2 is a building block in a larger design, but does not
> compile "on its own" because it uses too many pins and memory bits. Can

this
> cause the weird error in (2)?
>
>



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  #3 (permalink)  
Old 10-20-2003, 01:10 PM
Panic
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Posts: n/a
Default Re: Several Quartus II 3.0 questions


"Subroto Datta" <[email protected]> wrote [...]

Thank you *very* mutch!


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  #4 (permalink)  
Old 10-22-2003, 04:35 AM
Vaughn Betz
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Posts: n/a
Default Re: Several Quartus II 3.0 questions

>
> "Panic" <[email protected]> wrote in message
> news:[email protected]
> >
> > I'm a student working an a Altera EPXA1F484C1 FPGA, and I'm having some
> > problems I hope someone can help me with.
> >
> > 2. I get stuck-at errors...and I have no idea why. I get this warning:
> > "Warning: No clock transition on AESRoundSP-
> > 2:inst|lpm_dff0:inst5|lpm_ff:lpm_ff_component|dffs[127] register"
> > And this continues for all 128 flipflops. But they are clocked by the
> > "master clock". I have not created a clock signal, but the clock is named
> > clk, and then Quartus should assume that the signal is a clock, right?
> > Anyway, Quartus compiles my design without errors, but the summary tells

> me
> > that I'm not using any LEs or any memory bits...
> >
> > The AESRoundSP-2 is a building block in a larger design, but does not
> > compile "on its own" because it uses too many pins and memory bits. Can

> this
> > cause the weird error in (2)?
> >


The only times I've seen the warning above is when Quartus detects
that your clock signal will never toggle (i.e. it is either a logic
'0' or '1' all the time, due to the logic feeding it reducing to
that). This almost always indicates a design error. So I think this
is more basic than making clock settings etc. to tell Quartus your
clock frequency requirements and such -- Quartus has detected that
this circuit is almost certainly not what you want. You should
examine your HDL to see exactly what logic is generating this clock.

Vaughn
Altera
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  #5 (permalink)  
Old 10-23-2003, 07:53 PM
Guest
 
Posts: n/a
Default Re: Several Quartus II 3.0 questions

Vaughn Betz <[email protected]> wrote:
>>

> The only times I've seen the warning above is when Quartus detects
> that your clock signal will never toggle (i.e. it is either a logic
> '0' or '1' all the time, due to the logic feeding it reducing to
> that). This almost always indicates a design error. So I think this
> is more basic than making clock settings etc. to tell Quartus your
> clock frequency requirements and such -- Quartus has detected that
> this circuit is almost certainly not what you want. You should
> examine your HDL to see exactly what logic is generating this clock.


I had exactly this warning once when I was using the wrong library
(std_logic_signed instead of std_logic_unsigned !)

Roman

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