FPGA Central

I have this issue where i have a top level module say A.vhd that has a
state machine. I also have about 3 components - B.vhd, C.vhd and D.vhd
which i am going to use to make up my top level vhd module. I have process
statements in B,C and D and I want them to kick off at states 1,2 and 3
which I have defined in my main module.

so I have a 3 state FSM with states 1,2, and 3 in A.vhd and at state 1, I
want the process in b.vhd to kick off and at state 2 i want the process in
c.vhd to kick off and at state 3, I want the process in d.vhd to kick
off.
Can someone guide me through this pls?
thanks

"fpgawizz" <[email protected]> schrieb im Newsbeitrag
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> I have this issue where i have a top level module say A.vhd that has a
> state machine. I also have about 3 components - B.vhd, C.vhd and D.vhd
> which i am going to use to make up my top level vhd module. I have process
> statements in B,C and D and I want them to kick off at states 1,2 and 3
> which I have defined in my main module.
>
> so I have a 3 state FSM with states 1,2, and 3 in A.vhd and at state 1, I
> want the process in b.vhd to kick off and at state 2 i want the process in
> c.vhd to kick off and at state 3, I want the process in d.vhd to kick
> off.

Just use a signal and pass the data. Whats the point?

Regards
Falk