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05-21-2007, 05:01 PM
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Re: SelectIO banking rules
"LilacSkin" <[email protected]> wrote in message
news:[email protected] ps.com... > Hi, > > Can I drive a LCVMOS25 (input) and a LVTTL (input/output) in the same > bank even if there is VCCIO problems ? > > Thanks! Since the LVTTL requires 3.3V, the software won't let you do that. You can, perhaps, receive signals that aren't VCCIO compliant as outputs. Your data sheet will show what signals can be received at which VCCIO bank standard. 
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05-22-2007, 07:56 AM
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Re: SelectIO banking rules
That's my BANK 4:
I don't find the problem ! Pin Name Direction IO Standard IO_L49N_4 BIDIR LVTTL IO_L67N_4 BIDIR LVTTL IO_L07N_4 OUTPUT LVTTL IO_L19N_4 OUTPUT LVTTL IO_L37N_4 INPUT LVTTL IO_L43N_4 BIDIR LVTTL IO_L46N_4 BIDIR LVTTL IO_L49P_4 BIDIR LVTTL IO_L67P_4 BIDIR LVTTL IO_L05_4/No_Pair INPUT LVTTL IO_L07P_4/VREF_4 OUTPUT LVTTL IO_L19P_4 OUTPUT LVTTL IO_L37P_4 OUTPUT LVTTL IO_L43P_4 BIDIR LVTTL IO_L46P_4 BIDIR LVTTL IO_L55N_4 BIDIR LVTTL IO_L73N_4 BIDIR LVTTL IO_L08N_4 OUTPUT LVTTL IO_L25N_4 OUTPUT LVTTL IO_L38N_4 INPUT LVTTL IO_L47N_4 BIDIR LVTTL IO_L55P_4 TRISTATE LVTTL IO_L73P_4 BIDIR LVTTL IO_L08P_4 OUTPUT LVTTL IO_L25P_4 INPUT LVTTL IO_L26N_4 OUTPUT LVTTL IO_L38P_4 INPUT LVTTL IO_L47P_4 BIDIR LVTTL IO_L56N_4 BIDIR LVTTL IO_L68N_4 BIDIR LVTTL IO_L74N_4/GCLK3S INPUT LVCMOS25 IO_L20N_4 OUTPUT LVTTL IO_L39N_4 INPUT LVTTL IO_L26P_4 INPUT LVTTL IO_L44N_4 BIDIR LVTTL IO_L50_4/No_Pair BIDIR LVTTL IO_L56P_4 BIDIR LVTTL IO_L68P_4 BIDIR LVTTL IO_L74P_4/GCLK2P INPUT LVCMOS25 IO_L09N_4 OUTPUT LVTTL IO_L20P_4 OUTPUT LVTTL IO_L27N_4 OUTPUT LVTTL IO_L39P_4 OUTPUT LVTTL IO_L44P_4 BIDIR LVTTL IO_L53_4/No_Pair BIDIR LVTTL IO_L69N_4 BIDIR LVTTL IO_L75N_4/GCLK1S BIDIR LVTTL IO_L06N_4/VRP_4 OUTPUT LVTTL IO_L09P_4/VREF_4 OUTPUT LVTTL IO_L21N_4 OUTPUT LVTTL IO_L27P_4/VREF_4 INPUT LVTTL IO_L45N_4 BIDIR LVTTL IO_L48P_4 BIDIR LVTTL IO_L48N_4 BIDIR LVTTL IO_L57N_4 BIDIR LVTTL IO_L57P_4/VREF_4 BIDIR LVTTL IO_L69P_4/VREF_4 BIDIR LVTTL IO_L75P_4/GCLK0P INPUT LVTTL IO_L06P_4/VRN_4 OUTPUT LVTTL IO_L21P_4 OUTPUT LVTTL IO_L45P_4/VREF_4 BIDIR LVTTL IO_L54P_4 BIDIR LVTTL IO_L54N_4 BIDIR LVTTL
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05-22-2007, 02:05 PM
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Re: SelectIO banking rules
What a pretty list....
What device is this for? I suggested going to the data sheet to see what inputs can be powered by alternate VCCIOs. I can't go to the data sheet for you without knowing which device - at least which family - you're using. LilacSkin wrote: > That's my BANK 4: > I don't find the problem ! > > Pin Name Direction IO Standard > IO_L49N_4 BIDIR LVTTL > IO_L67N_4 BIDIR LVTTL > IO_L07N_4 OUTPUT LVTTL > IO_L19N_4 OUTPUT LVTTL > IO_L37N_4 INPUT LVTTL > IO_L43N_4 BIDIR LVTTL > IO_L46N_4 BIDIR LVTTL > IO_L49P_4 BIDIR LVTTL > IO_L67P_4 BIDIR LVTTL > IO_L05_4/No_Pair INPUT LVTTL > IO_L07P_4/VREF_4 OUTPUT LVTTL > IO_L19P_4 OUTPUT LVTTL > IO_L37P_4 OUTPUT LVTTL > IO_L43P_4 BIDIR LVTTL > IO_L46P_4 BIDIR LVTTL > IO_L55N_4 BIDIR LVTTL > IO_L73N_4 BIDIR LVTTL > IO_L08N_4 OUTPUT LVTTL > IO_L25N_4 OUTPUT LVTTL > IO_L38N_4 INPUT LVTTL > IO_L47N_4 BIDIR LVTTL > IO_L55P_4 TRISTATE LVTTL > IO_L73P_4 BIDIR LVTTL > IO_L08P_4 OUTPUT LVTTL > IO_L25P_4 INPUT LVTTL > IO_L26N_4 OUTPUT LVTTL > IO_L38P_4 INPUT LVTTL > IO_L47P_4 BIDIR LVTTL > IO_L56N_4 BIDIR LVTTL > IO_L68N_4 BIDIR LVTTL > IO_L74N_4/GCLK3S INPUT LVCMOS25 > IO_L20N_4 OUTPUT LVTTL > IO_L39N_4 INPUT LVTTL > IO_L26P_4 INPUT LVTTL > IO_L44N_4 BIDIR LVTTL > IO_L50_4/No_Pair BIDIR LVTTL > IO_L56P_4 BIDIR LVTTL > IO_L68P_4 BIDIR LVTTL > IO_L74P_4/GCLK2P INPUT LVCMOS25 > IO_L09N_4 OUTPUT LVTTL > IO_L20P_4 OUTPUT LVTTL > IO_L27N_4 OUTPUT LVTTL > IO_L39P_4 OUTPUT LVTTL > IO_L44P_4 BIDIR LVTTL > IO_L53_4/No_Pair BIDIR LVTTL > IO_L69N_4 BIDIR LVTTL > IO_L75N_4/GCLK1S BIDIR LVTTL > IO_L06N_4/VRP_4 OUTPUT LVTTL > IO_L09P_4/VREF_4 OUTPUT LVTTL > IO_L21N_4 OUTPUT LVTTL > IO_L27P_4/VREF_4 INPUT LVTTL > IO_L45N_4 BIDIR LVTTL > IO_L48P_4 BIDIR LVTTL > IO_L48N_4 BIDIR LVTTL > IO_L57N_4 BIDIR LVTTL > IO_L57P_4/VREF_4 BIDIR LVTTL > IO_L69P_4/VREF_4 BIDIR LVTTL > IO_L75P_4/GCLK0P INPUT LVTTL > IO_L06P_4/VRN_4 OUTPUT LVTTL > IO_L21P_4 OUTPUT LVTTL > IO_L45P_4/VREF_4 BIDIR LVTTL > IO_L54P_4 BIDIR LVTTL > IO_L54N_4 BIDIR LVTTL
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05-22-2007, 02:16 PM
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Re: SelectIO banking rules
On May 21, 10:49 am, LilacSkin <[email protected]> wrote:
> Hi, > > Can I drive a LCVMOS25 (input) and a LVTTL (input/output) in the same > bank even if there is VCCIO problems ? > > Thanks! It depends which device you are using. For some device, this is allowed. For some devices, you can't do this. This is usually well documented in the device user guide. ADEPT (http://home.comcast.net/~jimwu88/tools/adept/) can do some DRC on your pinout. Cheers, Jim
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05-23-2007, 12:25 PM
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Re: SelectIO banking rules
"John_H" <[email protected]> wrote in message news:gUB4i.4817$ns.251@trndny05... > What a pretty list.... > > What device is this for? > I suggested going to the data sheet to see what inputs can be powered by > alternate VCCIOs. I can't go to the data sheet for you without knowing > which device - at least which family - you're using. > A google of IO_L74P_4/GCLK2P site:xilinx.com would suggest 2vp7ff672 HTH, Syms. > > LilacSkin wrote: >> That's my BANK 4: >> IO_L67P_4 BIDIR LVTTL >> IO_L05_4/No_Pair INPUT LVTTL >> IO_L07P_4/VREF_4 OUTPUT LVTTL >> IO_L19P_4 OUTPUT LVTTL
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