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10-21-2005, 09:29 AM

bobrics

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RISC pipelining question

Hi,

Do you guys know the difference between the following two instructions:

LW 0(R1), F2
LW F2, 0(R1)

Are they equivalent?
If yes, then I assume on a regular 5-stage pipeline, R1+0 will be
executed in EX (ALU) stage and load to F2 will occur at MEM stage. Is
that correct to assume?

What I really need to know here is that for both commands, EX stage
takes care of 0+R1

Thank you

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