FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal


Go Back   FPGA Groups > NewsGroup > FPGA

FPGA comp.arch.fpga newsgroup (usenet)

LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 11-14-2007, 04:33 AM
Posts: n/a
Default REFCLK signal in Hard TEMAC core

I am troubleshooting a tri-mode ethernet interface utilizing the hard
MAC core provided in the VirtexFX series of FPGAs. I've instantiated
the hard TEMAC wrapper and the plb_TEMAC core that connects the plb
bus to the hard core. I'm still trying to read/write to the PHY's
registers over the management interface. I'm using GMII between the
MAC and PHY.

The hard temac wrapper core has a REFCLK input signal. The only
mention of this in the datasheet is regarding SGMII mode. REFCLK is
used for calibrating the IDELAYCTRL blocks needed for SGMII. I assumed
that for GMII, this clock was not needed. However, looking at the
plb_temac datasheet, they list an mhs file example for a dual MAC GMII
ethernet interface. In this example, they show REFCLK connected to the
plb clock.

Does anyone know if this signal is needed? Currently when I attempt a
PHY register read, I see both Management interrupts asset but never
see any data back. I have also not seen any activity on the MDIO/MDC
lines, so im led to believe this is a problem with how my cores are


Reply With Quote


Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On

Similar Threads
Thread Thread Starter Forum Replies Last Post
Xilinx Microblaze EDK and Virtex5/LXT TEMAC core? Helpme FPGA 0 09-22-2007 05:39 PM
V4FX60, hard temac, MPMC2 and SoDIMM morphiend FPGA 1 06-18-2007 05:03 PM
RGMII mode on V4 Hard Tri-EMAC core MM FPGA 10 04-19-2006 06:15 PM

All times are GMT +1. The time now is 02:32 AM.

Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved