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Old 11-10-2005, 12:08 PM
Kolja Sulimma
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Default Re: In Xilinx, how do I delay a signal by a fraction of a clock cycle?

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Frank schrieb:
> I am outputting a data with a clock 12.5MHz, which will latch the data
> into external chip whose input delay is unknown.

Other posters helped you with your suggested approach. But I doubt that
what you are trying to do is neccessary.

Whtat do you men by input delay? If data is clocked into a device
usually there are two important parameters: Setup and hold time.
It should be possible to find out what these are for your device. If you
give us a part number maybe someone even knows the values.

Also, for virtually all devices that I know of both parameters are an
order of magnitude smaller than 40ns. Therefore if you register the data
at the opposite edge of your clock you are very likely meeting both
requirements.

Also, hold times tend to be very small. Probably smaller than the Tco
parameter of the FPGA. If this is true you can achieve a simpler design
by registering the data with the same clock edge for both devices.

Kolja Sulimma
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