FPGA Central

Eric, what makes you think that 62 MHz I/O transfer is a problem?
You can easily go twice as fast...

Peter Alfke, Xilinx
=========================
Eric wrote:
>
> Hello! I'm trying to move 125 MB/sec bidirectionally off a daughter
> card, for a total of 250 MB/sec. I worry that even if I double the 8
> bit bus in each direction to 16-bits (32 data pins todal) I'll still
> be pushing a single-ended signal across a connector at 62.5 MHz. I
> can't go wider because I run out of pins on my QFP.
>
> I've started looking at LVDS, but it seems that xilinx has very little
> information on how to actually _use_ lvds in a project. National has
> some great app notes, but they're largely targeted at the national
> family of SERDES products. Can anyone offer any suggestions for
> high-speed multi-board data transfer between FPGAs? Has anyone ever
> tried building a SerDes in a spartan-IIE, and if so, what kinds of
> speeds have you been able to get?
>
> Thanks for the help!
> ...Eric

> Eric wrote:
> >
> > Hello! I'm trying to move 125 MB/sec bidirectionally off a daughter
> > card, for a total of 250 MB/sec. I worry that even if I double the 8
> > bit bus in each direction to 16-bits (32 data pins todal) I'll still
> > be pushing a single-ended signal across a connector at 62.5 MHz. I
> > can't go wider because I run out of pins on my QFP.
> >
> > I've started looking at LVDS, but it seems that xilinx has very little
> > information on how to actually _use_ lvds in a project. National has
> > some great app notes, but they're largely targeted at the national
> > family of SERDES products. Can anyone offer any suggestions for
> > high-speed multi-board data transfer between FPGAs? Has anyone ever
> > tried building a SerDes in a spartan-IIE, and if so, what kinds of
> > speeds have you been able to get?
> >
> > Thanks for the help!
> > ...Eric
Peter Alfke <[email protected]> wrote in message news:<[email protected]>...
> Eric, what makes you think that 62 MHz I/O transfer is a problem?
> You can easily go twice as fast...
>
> Peter Alfke, Xilinx
> =========================


I'm too poor to buy an IBIS simulator I've been reading all sorts
of data sheets and app notes on LVDS that have made me worry about any
sort of single-ended signals one can reliably send over a short bus.
I read that PCI has really tight timings and is evidently really hard
to design for; it's only 33 MHz. Sure, it's a bus with multiple cards,
but AGP is a single card in a single slot, and only runs at 66 MHz. I
feared that if "real" EEs (instead of us biologists that just play
them when we need equiment that doesn't exist) don't want to push a
card interconnect above 66 Mhz, there must be a good reason.

So I'm trying to figure out what I can reasonably expect from a
4-layer FR4 board and a 68-pin high-density mini-D connector. This is
my first high-speed interconnect project, and it may just be paranoia.
Are you suggesting I shouldn't lose too much sleep over a ~125 MHz
single-ended bus covering a distance of 6" or so? or should I stick to
differential signaling for those types of speeds? I'd love to just
make my bus wider, but I run out of IOs on my Spartan-IIE PQFP and I
can't afford to have someone put down a BGA on a PCB.

Ahh, the joys of low-cost student design !

Thanks again for all the help,
...Eric

Read the bible - "High Speed Digital Design", by Johnson and Graham !

Dave

"Eric" <[email protected]> wrote in message news:bfab508[email protected] om...
> > Eric wrote:
> > >
> > > Hello! I'm trying to move 125 MB/sec bidirectionally off a daughter
> > > card, for a total of 250 MB/sec. I worry that even if I double the 8
> > > bit bus in each direction to 16-bits (32 data pins todal) I'll still
> > > be pushing a single-ended signal across a connector at 62.5 MHz. I
> > > can't go wider because I run out of pins on my QFP.
> > >
> > > I've started looking at LVDS, but it seems that xilinx has very little
> > > information on how to actually _use_ lvds in a project. National has
> > > some great app notes, but they're largely targeted at the national
> > > family of SERDES products. Can anyone offer any suggestions for
> > > high-speed multi-board data transfer between FPGAs? Has anyone ever
> > > tried building a SerDes in a spartan-IIE, and if so, what kinds of
> > > speeds have you been able to get?
> > >
> > > Thanks for the help!
> > > ...Eric
> Peter Alfke <[email protected]> wrote in message news:<[email protected]>...
> > Eric, what makes you think that 62 MHz I/O transfer is a problem?
> > You can easily go twice as fast...
> >
> > Peter Alfke, Xilinx
> > =========================
>
>
> I'm too poor to buy an IBIS simulator I've been reading all sorts
> of data sheets and app notes on LVDS that have made me worry about any
> sort of single-ended signals one can reliably send over a short bus.
> I read that PCI has really tight timings and is evidently really hard
> to design for; it's only 33 MHz. Sure, it's a bus with multiple cards,
> but AGP is a single card in a single slot, and only runs at 66 MHz. I
> feared that if "real" EEs (instead of us biologists that just play
> them when we need equiment that doesn't exist) don't want to push a
> card interconnect above 66 Mhz, there must be a good reason.
>
> So I'm trying to figure out what I can reasonably expect from a
> 4-layer FR4 board and a 68-pin high-density mini-D connector. This is
> my first high-speed interconnect project, and it may just be paranoia.
> Are you suggesting I shouldn't lose too much sleep over a ~125 MHz
> single-ended bus covering a distance of 6" or so? or should I stick to
> differential signaling for those types of speeds? I'd love to just
> make my bus wider, but I run out of IOs on my Spartan-IIE PQFP and I
> can't afford to have someone put down a BGA on a PCB.
>
> Ahh, the joys of low-cost student design !
>
> Thanks again for all the help,
> ...Eric

[snip]

> I read that PCI has really tight timings and is evidently really hard
> to design for; it's only 33 MHz. Sure, it's a bus with multiple cards,
> but AGP is a single card in a single slot, and only runs at 66 MHz. I
> feared that if "real" EEs (instead of us biologists that just play
> them when we need equiment that doesn't exist) don't want to push a
> card interconnect above 66 Mhz, there must be a good reason.

[snip]

The hard part in "33 MHz" PCI is a 7 ns path on the PCI IRDY# and TRDY#
control signals to output enables on the FPGA. So, instead of a "33 MHz"
problem, you really have a 143 MHz" design challenge. The issue is related
to propagation time within the FPGA and not related to signal integrity
issues.

BTW, Spartan-IIE fully supports 66 MHz and 64-bit PCI and is available in a
proven LogiCORE solution.
http://www.xilinx.com/partinfo/pci/xcvpci64_32ds.pdf

--------------------------------
Steven K. Knapp
Spartan-3/II/IIE FPGAs
http://www.xilinx.com/spartan3
---------------------------------
Spartan-3: Make it Your ASIC