FPGA Central

On Wed, 31 Oct 2007 04:05:57 -0700, Jim Thompson
<[email protected]> wrote:

>On Tue, 30 Oct 2007 21:12:11 -0700, "Mike" <[email protected]> wrote:
>
>>Finally, proof positive! The PFD fails to detect phase! I'm sure you will be
>>happy to know this important information.
>>
>>http://rfdesign.com/vlf_to_uhf/time_...207/index.html
>>
>>To begin, the author does acknowledge that the PFD detects frequency (at
>>least you didn't get everything wrong):
>>
>>"When the frequency difference is small, one of the currrent sources will be
>>turned on more often than the other. Therefore, the PFD does function as a
>>frequency detector."
>>
>>So far, so good. At least you didn't mess everything up. But then, he
>>delivers the shocker! The PFD does NOT actually detect phase! It's true!
>>
>>"To test whether the PFD is a true phase detector, a fixed-frequency signal
>>can be supplied simultaneously to Fvco and to a variable-delay circuit whose
>>output feeds Fref. This will produce a variable phase delay. With the output
>>of the PFD connected to the LPF as before, the measured result shows that
>>the PFD is not a true linear phase detector, because the output of the LPF
>>can only stay at either the saturated high or low state, depending upon
>>which signal has a phase lead over the other."
>>
>>As if that's not devastating enough, he delivers his final conclusion about
>>the PFD:
>>
>>"The PFD is thus seen to be an arrival-time detector, instead of a
>>phase-frequency detector, because it provides a steady-state output that
>>provides both polarity and magnitude of the measured time difference."
>>
>>Wow! Can you believe it? I know I can.
>>
>>I've been using PFDs for many years, and thought I knew something about
>>them, but the author of this article has far more experience than I do, and
>>has even started a company to commercialize his discovery. He simply can't
>>be argued with!
>>
>>I'm sorry Jim, but after umpteen years, the jig is up. Forget the design
>>wins, and all the successful implementations. It didn't really work after
>>all.
>>
>>Better luck next time.
>>
>>-- Mike --
>>
>Sno-o-o-ort!
>
>Just goes to show you to what crap the USPTO will award a patent.
>
>I'll read it carefully upon return from hospital.
>
> ...Jim Thompson


I "invented" this last week. FPGAs aren't very good at implementing
the classic charge pump.

http://s2.supload.com/free/PFD.jpg/view/

The outputs here are just hard (not tri-state) logic outputs, driven
directly by the up/down flipflops in the pfd circuit. It's nicely
symmetric.

John

> I "invented" this last week. FPGAs aren't very good at implementing
> the classic charge pump.
>
> http://s2.supload.com/free/PFD.jpg/view/
>
> The outputs here are just hard (not tri-state) logic outputs, driven
> directly by the up/down flipflops in the pfd circuit. It's nicely
> symmetric.
>
> John- Zitierten Text ausblenden -
>
> - Zitierten Text anzeigen -

But the Inventor mentioned the additional jitter due to uncorrelated
noise of the 2 PFD outputs and their summation in your example, and
the evil glitches due to unmatched symmetry and parasitic coupling of
the digital to the analog !
This must be worth a patent.

Having read

http://www.keystonesemiconductor.com..._releases.html

i now fear the evil glitch and deadtime jitter to corrupt my computer
before global warming blasts icebergs and blazes glaciers.

On Wed, 31 Oct 2007 09:38:41 -0700, [email protected] wrote:

>> I "invented" this last week. FPGAs aren't very good at implementing
>> the classic charge pump.
>>
>> http://s2.supload.com/free/PFD.jpg/view/
>>
>> The outputs here are just hard (not tri-state) logic outputs, driven
>> directly by the up/down flipflops in the pfd circuit. It's nicely
>> symmetric.
>>
>> John- Zitierten Text ausblenden -
>>
>> - Zitierten Text anzeigen -
>
>But the Inventor mentioned the additional jitter due to uncorrelated
>noise of the 2 PFD outputs and their summation in your example, and
>the evil glitches due to unmatched symmetry and parasitic coupling of
>the digital to the analog !
>This must be worth a patent.
>
>Having read
>
>http://www.keystonesemiconductor.com..._releases.html
>
>i now fear the evil glitch and deadtime jitter to corrupt my computer
>before global warming blasts icebergs and blazes glaciers.

Oh, the guy is clearly a lunatic, and an amateur lunatic to boot. His
writing is hilarious.

But the dual-diode thing solves a couple of problems using an FPGA as
a phase-frequency detector.

John

Hi, John
I suppose you know about the old Xilinx app note:
http://direct.xilinx.com/bvdocs/appnotes/xapp028.pdf
which would benefit from your diode trick.
Cheers
Peter Alfke, Xilinx Applications

On Oct 31, 10:32 am, John Larkin
<[email protected]> wrote:
> On Wed, 31 Oct 2007 09:38:41 -0700, [email protected] wrote:
> >> I "invented" this last week. FPGAs aren't very good at implementing
> >> the classic charge pump.
>
> >>http://s2.supload.com/free/PFD.jpg/view/
>
> >> The outputs here are just hard (not tri-state) logic outputs, driven
> >> directly by the up/down flipflops in the pfd circuit. It's nicely
> >> symmetric.
>
> >> John- Zitierten Text ausblenden -
>
> >> - Zitierten Text anzeigen -
>
> >But the Inventor mentioned the additional jitter due to uncorrelated
> >noise of the 2 PFD outputs and their summation in your example, and
> >the evil glitches due to unmatched symmetry and parasitic coupling of
> >the digital to the analog !
> >This must be worth a patent.
>
> >Having read
>
> >http://www.keystonesemiconductor.com..._releases.html
>
> >i now fear the evil glitch and deadtime jitter to corrupt my computer
> >before global warming blasts icebergs and blazes glaciers.
>
> Oh, the guy is clearly a lunatic, and an amateur lunatic to boot. His
> writing is hilarious.
>
> But the dual-diode thing solves a couple of problems using an FPGA as
> a phase-frequency detector.
>
> John

Peter Alfke wrote:
> Hi, John
> I suppose you know about the old Xilinx app note:
> http://direct.xilinx.com/bvdocs/appnotes/xapp028.pdf
> which would benefit from your diode trick.
> Cheers
> Peter Alfke, Xilinx Applications

The tristate drive is seen in many PFD's.
Tristate works well, but does float the FPGA pin
at the Opmap Bias point, and is also a noise-injection
point.
Also either the Diode, or Tristate directly couple
the FPGA Vcc and GND noise into the integrator (when ON)

So the "purists PFD", would use a TinyLogic analog Switch,
[example of 2 in one package : 74LVC2G66 ]
and keep the Hi-Z integrator node tiny, and shielded from
digital charge injection, and power supply noise.

Also, some designs have deliberate overlap in the PFD
impulses, as that avoids a dead-band, which can give
higher spurious noise spurs.

-jg

On Wed, 31 Oct 2007 11:22:20 -0700, Peter Alfke <[email protected]>
wrote:

>Hi, John
>I suppose you know about the old Xilinx app note:
>http://direct.xilinx.com/bvdocs/appnotes/xapp028.pdf
>which would benefit from your diode trick.
>Cheers
>Peter Alfke, Xilinx Applications

The diode thing allows true overlap (ie, zero deadband operation)
without worrying about relative pfet/nfet drive strengths or tristate
enable times. It also eliminates a more subtle problem related to pin
capacitances, which would add yet another nonlinearity to the already
nonlinear xapp circuit.

Skyworks makes some 0.22 pF, SC79 schottkies that would be ideal here.

Loop gain doubles in the overlap region, but that's easy to deal with.
It's sure better than a flat spot.

The opamp situation can be interesting.

John

John Larkin wrote:

> On Wed, 31 Oct 2007 11:22:20 -0700, Peter Alfke <[email protected]>
> wrote:
>
>
>>Hi, John
>>I suppose you know about the old Xilinx app note:
>>http://direct.xilinx.com/bvdocs/appnotes/xapp028.pdf
>>which would benefit from your diode trick.
>>Cheers
>>Peter Alfke, Xilinx Applications
>
>
> The diode thing allows true overlap (ie, zero deadband operation)
> without worrying about relative pfet/nfet drive strengths or tristate
> enable times. It also eliminates a more subtle problem related to pin
> capacitances, which would add yet another nonlinearity to the already
> nonlinear xapp circuit.
>
> Skyworks makes some 0.22 pF, SC79 schottkies that would be ideal here.
>
> Loop gain doubles in the overlap region, but that's easy to deal with.
> It's sure better than a flat spot.

Yes, better systems take effort to avoid any dead-band

>
> The opamp situation can be interesting.

With the single-resistor drawn in the Xilinx app note, it gets worse
- there is buffer contention during that (short) time = more unknowns

-jg

"Peter Alfke" <[email protected]> wrote in message
news:[email protected] oups.com...
> Hi, John
> I suppose you know about the old Xilinx app note:
> http://direct.xilinx.com/bvdocs/appnotes/xapp028.pdf
> which would benefit from your diode trick.
> Cheers
> Peter Alfke, Xilinx Applications
>
Guys,
Beware of XAPP028...

From
http://groups.google.com/groups/sear...comp.arch.fpga

Quote:-
A small note of caution when using Peter's XAPP028 in Virtex II. As
well as constraining the logic to the CLBs shown in the app note, make
sure you specify a MAXSKEW attribute on the reference signal and
feedback signal to the circuit. I use 100ps. Without this the circuit
can occasionally malfunction depending on the place and route. (These
are the signals called 'from VCO divided by N' and 'from reference
frequency'.)
There was no problem when this circuit was used on older FPGAs
where the routing to the F and G lookup tables in a single CLB was
guaranteed to have low skew. In Virtex II this is no longer the case
and a single signal that goes to both the F and G inputs of a CLB can
have significant skew if not constrained. This can cause the circuit
of XAPP28 to misbehave.

HTH., Syms.

On Oct 31, 3:47 pm, "Symon" <[email protected]> wrote:
> "Peter Alfke" <[email protected]> wrote in message
>
> news:[email protected] oups.com...> Hi, John
> > I suppose you know about the old Xilinx app note:
> >http://direct.xilinx.com/bvdocs/appnotes/xapp028.pdf
> > which would benefit from your diode trick.
> > Cheers
> > Peter Alfke, Xilinx Applications
>
> Guys,
> Beware of XAPP028...
>
> Fromhttp://groups.google.com/groups/search?q=xapp028+symon+MAXSKEW+group%...
>
> Quote:-
> A small note of caution when using Peter's XAPP028 in Virtex II. As
> well as constraining the logic to the CLBs shown in the app note, make
Thanks, Syms, for pointing this out.
I published this in 1990, in the XC3000 era, and I was proud of
packing it so nicely.
Your comment makes me retire the circuit, but it will unfortunately
survive on the internat...
Peter

> sure you specify a MAXSKEW attribute on the reference signal and
> feedback signal to the circuit. I use 100ps. Without this the circuit
> can occasionally malfunction depending on the place and route. (These
> are the signals called 'from VCO divided by N' and 'from reference
> frequency'.)
> There was no problem when this circuit was used on older FPGAs
> where the routing to the F and G lookup tables in a single CLB was
> guaranteed to have low skew. In Virtex II this is no longer the case
> and a single signal that goes to both the F and G inputs of a CLB can
> have significant skew if not constrained. This can cause the circuit
> of XAPP28 to misbehave.
>
> HTH., Syms.